Arm Cortex-M3 Processor Operation; Arm Cortex-M3 Processor Related Documents - Analog Devices ADuCM355 Hardware Reference Manual

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ARM CORTEX-M3 PROCESSOR OPERATION

Several Arm Cortex-M3 processor components are flexible in their implementation. This section details the implementation of these
components in the ADuCM355.
Serial Wire Debug
The ADuCM355 only supports the serial wire interface via the SWCLK and SWDIO pins. The device does not support the 5-wire, Joint
Action Test Group (JTAG) interface. The SWCLK pin is driven by the debug probe. The SWDIO signal is a bidirectional signal that can
be driven by the debug probe or target, depending on the protocol phase.
NVIC
The Arm Cortex-M3 processor includes an NVIC, which offers several features, as follows:

Nested interrupt support

Vectored interrupt support

Dynamic priority changes support

Interrupt masking
In addition, the NVIC has an NMI input. The NVIC is implemented on the ADuCM355, and more details are available in the System
Exceptions and Peripheral Interrupts section.
Wake-Up Interrupt Controller
The ADuCM355 has a modified WIC that provides the lowest possible power-down current. See the Power Management Unit section
for details.
It is not recommended to enter power saving mode when servicing an interrupt. However, if the device enters power saving mode when
servicing an interrupt, it can only be woken up by a higher priority interrupt source.

ARM CORTEX-M3 PROCESSOR RELATED DOCUMENTS

The following list contains documentation related to the Arm Cortex-M3:

Arm Cortex-M3 Processor Technical Reference Manual Revision r2p1 (DDI 0337)

Arm Processor Cortex-M3 (AT420) and Cortex-M3 with ETM (AT425) Software Developers Errata Notice

Armv7-M Architecture Reference Manual (DDI 0403) with Errata Markups

Arm Debug Interface Architecture Specification ADIV5.0 to ADIV5.2 (IHI 0031)

PrimeCell μDMA Controller (PL230) Technical Reference Manual, Revision r0p0 (DDI 0417)
ADuCM355
Rev. B | Page 36 of 312
Hardware Reference Manual