Analog Devices ADuCM355 Hardware Reference Manual page 268

UG-1262
undefined results can occur. By default, the counter is reloaded automatically when generating the interrupt signal. If GPTx_CTL, Bit 7 is
set to 1, the counter is also reloaded when user code writes GPTx_CLRINT, which allows user changes to GPTx_LOAD to take effect
immediately instead of waiting until the next timeout.
The timer interval is calculated as follows:
If the timer is set to count down,
Interval = (GPTx_LOAD × Prescaler)/Clock Source
For example, if GPTx_LOAD = 0x100, prescaler = 4, and clock source = high frequency oscillator, the interval is 39.38 μs (where high
frequency oscillator = 26 MHz).
If the timer is set to count up,
Interval = ((Full Scale − GPTx_LOAD) × Prescaler)/Clock Source
Asynchronous Clock Source
Timers are started by setting the enable bit (GPTx_CTL, Bit 4) to 1 in the control register of the corresponding timer. However, when the
timer clock source is the low frequency oscillator, some precautions must be taken.

Do not write to GPTx_CTL if GPTx_STAT, Bit 6 is set. GPTx_STAT must be read prior to configuring GPTx_CTL. When
GPTx_STAT, Bit 6 is cleared, the register can be modified, ensuring that synchronizing the timer control between the processor and
the timer clock domains is complete. GPTx_STAT, Bit 6 is the timer busy status bit.

After clearing the interrupt in GPTx_CLRINT, ensure that the register write has completed before returning from the interrupt
handler. Use the data synchronization barrier (DSB) instruction if necessary and check that GPTx_STAT, Bit 7 = 0, as follows:
__asm void asmDSB()
{
nop
DSB
BX LR
}

The value of a counter can be read at any time by accessing its value register (GPTx_CURCNT). In an asynchronous configuration,
GPTx_CURCNT must always be read twice. If the two readings are different, this register must be read a third time to determine the
correct value.
GPTx_STAT must be read prior to writing to any timer register after setting or clearing the enable bit. When GPTx_STAT, Bit 7 is
cleared, registers can be modified, which ensures that the timer has completed synchronization between the processor and the timer
clock domains. The typical synchronization time is two timer clock periods.
The GPTx_CTL register enables the counter, selects the mode, selects the prescale value, and controls the event capture function.
Capture Event Function
The general-purpose timers can capture several interrupt events. These events are shown in Table 341. Any one of the events associated
with a general-purpose timer can cause a capture of the 16-bit GPTx_CURCNT register into the 16-bit GPTx_CAPTURE register.
GPTx_CTL has a 5-bit field that can select which event to capture.
When the selected interrupt event occurs, the GPTx_CURCNT register is copied into the GPTx_CAPTURE register. When
GPTx_STAT, Bit 1 is set, it indicates that a capture event is pending. The bit is cleared by writing 1 to GPTx_CLRINT, Bit 1. The
GPTx_CAPTURE register also holds its value and cannot be overwritten until a 1 is written to GPTx_CLRINT, Bit 1.
ADuCM355
Rev. B | Page 268 of 312
Hardware Reference Manual
(27)
(28)