Bus Error Clear Register; Per Channel Bus Error Register; Per Channel Invalid Descriptor Clear Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual

BUS ERROR CLEAR REGISTER

Address: 0x40010048, Reset: 0x00000000, Name: ERR_CLR
Table 210. Bit Descriptions for ERR_CLR
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN

PER CHANNEL BUS ERROR REGISTER

Address: 0x4001004C, Reset: 0x00000000, Name: ERRCHNL_CLR
Table 211. Bit Descriptions for ERRCHNL_CLR
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN

PER CHANNEL INVALID DESCRIPTOR CLEAR REGISTER

Address: 0x40010050, Reset: 0x00000000, Name: INVALIDDESC_CLR
Table 212. Bit Descriptions for INVALIDDESC_CLR
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN
Description
Reserved.
Bus Error Status. This register is used to read and clear the DMA bus error status.
The error status is set if the controller encountered a bus error while performing
a transfer or when it reads an invalid descriptor (whose cycle control is 0b000). If
a bus error occurs or an invalid cycle control is read on a channel, that channel is
automatically disabled by the controller. The other channels are unaffected.
Write 1 to clear bits.
0 When read, no bus error or an invalid cycle control has occurred. When written,
no effect.
1 When read, a bus error or invalid cycle control is pending. When written, bit is
cleared.
Description
Reserved.
Per Channel Bus Error Status and Per Channel Bus Error Clear. This register is used
to read and clear the per channel DMA bus error status. The error status is set if
the controller encountered a bus error while performing a transfer. If a bus error
occurs on a channel, that channel is automatically disabled by the controller. The
other channels are unaffected. Write 1 to clear bits.
0 When read as 0, no bus error has occurred. When written as 0, no effect.
1 When read as 1, a bus error control is pending. When written as 1, bit is cleared.
Description
Reserved.
Per Channel Invalid Descriptor Status and Per Channel Invalid Descriptor Status
Clear. This register is used to read and clear the per channel DMA invalid
descriptor status. The per channel invalid descriptor status is set if the controller
reads an invalid descriptor (whose cycle control is 0b000). If the controller reads
invalid cycle control for a channel, that channel is automatically disabled by the
controller. The other channels are unaffected. Write 1 to clear bits.
0 When read as 0, no invalid cycle control has occurred. When written as 0, no effect.
1 When read as 1, an invalid cycle control is pending. When written as 1, bit is cleared.
Rev. B | Page 181 of 312
UG-1262
Reset Access
0x00 R
0x000000 R/W1C
Reset Access
0x00 R
0x000000 R/W1C
Reset Access
0x00 R
0x000000 R/W1C