Register Details: Analog Die Circuitry; Afe Configuration Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual

REGISTER DETAILS: ANALOG DIE CIRCUITRY

AFE CONFIGURATION REGISTER

Address: 0x400C2000, Reset: 0x00080000, Name: AFECON
Specific bits in this registers are relevant to particular blocks in the analog die. The relevant bits for each block are as follows:

Bits relevant to the ADC block are Bit 16, Bit 15, Bit 13, Bit 12, Bit 8, Bit 7, and Bit 5.

Bits relevant to the high speed TIA block are Bit 11 and Bit 5.

Bits relevant to the high speed DAC block are Bit 21, Bit 20, Bit 14, Bit 10, Bit 9, and Bit 5.
Table 52. Bit Descriptions for AFECON
Bits Bit Name
[31:22] Reserved
21 HSDACBUFEN
20 HSDACREFEN
19 ALDOILIMITEN
[18:17] Reserved
16 SINC2EN
15 DFTEN
14 WAVEGENEN
13 TEMPCONVEN0
12 TEMPSENSEN0
11 HSTIAEN
10 INAMPEN
Settings Description
Reserved.
Enable DC DAC Buffer. Enable the buffer for the high impedance output
of the dc DAC.
0 Disable dc DAC buffer.
1 Enable dc DAC buffer.
High Speed DAC Reference Enable.
0 Reference disable. Clear to 0 to disable the high speed DAC reference.
1 Reference enable. Set to 1 to enable the high speed DAC reference.
Analog LDO Buffer Current Limiting. Enable the AFE analog LDO buffer
current limiting. If enabled, LDO buffer current limiting limits the current
drawn from an external battery when charging the capacitor on AVDD_REG.
0 Analog LDO buffer current limiting enabled.
1 Analog LDO buffer current limiting disabled.
Reserved.
ADC Output 50 Hz or 60 Hz Filter Enable. Enable 50 Hz or 60 Hz supply
rejection filter. When the sinc2 digital filter is used, clear this bit and set it
before restarting ADC conversions.
0 Supply rejection filter disabled. Disable sinc2 (50 Hz/60 Hz digital filter).
Disable this bit for impedance measurements.
1 Supply rejection filter enabled. Enable sinc2 (50 Hz/60 Hz digital filter).
DFT Hardware Accelerator Enable. Enable the DFT hardware acceleration
block.
0 DFT hardware accelerator disabled.
1 DFT hardware accelerator enabled.
Waveform Generator Enable. Enable waveform generator.
0 Waveform generator disabled.
1 Waveform generator enabled.
ADC Temperature Sensor 0 Convert Enable. Enables ADC temperature
channel conversion. When the temperature conversion is complete, the
result is available in the TEMPSENSDAT0 register. After the conversion, this
bit is reset to 0.
0 Temperature Channel 0 reading disabled.
1 Temperature Channel 0 reading enabled.
ADC Temperature Sensor 0 Channel Enable. Enable temperature sensor.
0 Temperature sensor disabled. The temperature sensor is powered down.
1 Temperature sensor enabled. The temperature sensor is powered up but no
temperature readings are performed unless the TEMPCONVEN0 bit = 1.
Enable High Speed TIA.
0 High speed TIA disabled.
1 High speed TIA enabled.
Enable Excitation Instrumentation Amplifier on the High Speed DAC
Output. Enables instrumentation amplifier.
0 High speed DAC programmable instrumentation amplifier disabled.
1 High speed DAC programmable instrumentation amplifier enabled.
Rev. B | Page 55 of 312
UG-1262
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x1 R/W
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W