Analog Devices ADuCM355 Hardware Reference Manual page 257

ADuCM355 Hardware Reference Manual
Interrupts
The UART peripheral has one interrupt output to the interrupt controller for both receive and transmit interrupts. The COMIIR register
must be read by the software to determine the cause of the interrupt. In DMA mode, the break interrupt is not available. When receiving
in input or output mode, the interrupt is generated for the following cases:

COMRX is full.

Receive overflow error.

Receive parity error.

Receive framing error.

Receive FIFO timeout if FIFO (16550 UART) is enabled.

Break interrupt (UART input pin UART_SIN held low).

COMTX empty.
Buffer Requirements
This UART is double buffered, meaning it has a hold register and a shift register.
FIFO Mode (16550 UART)
The 16-byte deep transmit FIFO and receive FIFO are implemented. Therefore, the UART is compatible with the industry-standard
16550 UART. By default, these FIFOs are disabled. To enable them, set COMFCR, Bit 0. When enabled, the internal FIFOs allow
16 bytes to be stored in both the receive and transmit modes of operation, and 3 bits of error data per byte in the receive FIFO.
The interrupt and DMA trigger for the number of bytes received into the receive FIFO is programmed via COMFCR, Bits[7:6]. The
DMA requests are programmed by the COMFCR, Bit 3. If this bit is set, the FIFO must also be enabled by setting COMFCR, Bit 0 to 1. If
the remaining bytes in a packet are less than the interrupt trigger number, a timeout interrupt occurs. This timeout is indicated by
COMIIR, Bits[3:1] = 0b110. This timeout period is equal to the period of four consecutive characters where a single character time is one
start bit, n data bits, one parity bit, and one stop bit, where n depends on the word length selected by COMLCR, Bits[1:0].
DMA Mode
In DMA mode, user code does not move data to and from the UART. DMA request signals entering the external DMA block indicate
that the UART is ready to transmit or receive data. These DMA request signals can be disabled in the COMIEN register.
Automatic Baud Rate Detection
The automatic baud detection (ABD) block is used to match the baud rates of two UART devices automatically. The receiver must be
enabled to detect the mode before a common baud rate is configured. The COMACR, Bit 0 enables the receiver to work in ABD mode. A
20-bit counter logic counts the number of cycles between the programmed rising or falling edge and another rising or falling edge. An
interrupt is generated after the expected edges are reached. The counter can overflow and generate a timeout interrupt, such as when
there is a continuous break condition or no expected edges.
For example, if the data byte being received is 0x0D (0b00001101, resulting in a carriage return) in 8-bit mode without a parity bit, LSB
first, each bit reads as DATA0 = 1, DATA1 = 0, DATA2 = 1, DATA3 = 1, and DATA4 = DATA5 = DATA6 = DATA7 = 0.
There are three falling edges and three rising edges. The COMACR, Bits[6:4] can be written to 1 decimal (second edge), and COMACR,
Bits[11:8] can be written to 5 decimal (sixth edge) to count between the first rising edge and the second rising edge. See Figure 63 for more
details.
0µs
SIGNAL
UART_SOUT
PCLK
0
ABD
250µs
PCLK CYCLES FROM
START DATA0 DATA1
1 2 3 4
Figure 63. Autobaud Rate Example
500µs
x y
TH TH
EDGE TO EDGE
DATA2 DATA3
5 6 7
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750µs
DATAn STOP
xx
UG-1262
1000µs