External Wake-Up Interrupt Status Register; External Interrupt Clear Register; Nonmaskable Interrupt Clear Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

EXTERNAL WAKE-UP INTERRUPT STATUS REGISTER

Address: 0x4004C084, Reset: 0x00000000, Name: XINT_EXT_STAT
Table 47. Bit Descriptions for XINT_EXT_STAT
Bits Bit Name
[31:6] Reserved
5 STAT_UART_RXWKUP
4 RESERVED
3 STAT_EXTINT3
2 RESERVED
1 STAT_EXTINT1
0 Reserved

EXTERNAL INTERRUPT CLEAR REGISTER

Address: 0x4004C090, Reset: 0x00000000, Name: XINT_CLR
Table 48. Bit Descriptions for XINT_CLR
Bits Bit Name Settings
[31:6] Reserved
5 UART_RX_CLR
4 IRQ3
[3:2] Reserved
1 IRQ1
0 Reserved

NONMASKABLE INTERRUPT CLEAR REGISTER

Address: 0x4004C094, Reset: 0x00000000, Name: XINT_NMICLR
Table 49. Bit Descriptions for XINT_NMICLR
Bits Bit Name Settings
[31:1] Reserved
0 CLR
Settings Description
Reserved.
Interrupt Status Bit for P0.11/UART_SIN Wake-Up Interrupt. Read only
register bit. Cleared by writing 1 to XINT_CLR, Bit 5.
0 P0.11/UART_SIN wakeup did not generate the interrupt.
1 P0.11/UART_SIN wakeup generated the interrupt.
Reserved.
Interrupt Status Bit for External Interrupt 3. This bit is valid if there is an INTC
interrupt from the AFE die to the digital die.
0 External Interrupt 3 did not generate the interrupt.
1 External Interrupt 3 generated the interrupt.
Reserved.
Interrupt Status Bit for External Interrupt 1. This bit is valid if there is an
interrupt asserted on SYS_WAKE. Cleared by writing 1 to XINT_CLR, Bit 1.
Read only register bit.
0 External Interrupt 1 did not generate the interrupt.
1 External Interrupt 1 generated the interrupt.
Reserved.
Description
Reserved.
External Interrupt Clear for P0.11/UART_SIN Wake-Up Interrupt. Set to 1 to clear the
interrupt status flag. Cleared automatically by hardware.
External Interrupt 3. Set to 1 to clear the interrupt status flag. Cleared automatically
by hardware.
Reserved.
External Interrupt 1. Set to 1 to clear the interrupt status flag. Cleared automatically
by hardware.
Reserved.
Description
Reserved.
NMI Clear. Set to 1 to clear an interrupt status flag when the NMI interrupt is set. Cleared
automatically by hardware.
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ADuCM355 Hardware Reference Manual
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R
Reset Access
0x0 R
0x0 R/W