Analog Devices ADuCM355 Hardware Reference Manual page 293

ADuCM355 Hardware Reference Manual
Bits Bit Name Settings
11 WSYNCALM0
10 WSYNCCNT1
9 WSYNCCNT0
8 WSYNCSR0
7 WSYNCCR0
6 WPENDINT
5 WSYNCINT
4 WPNDERRINT
Description
Synchronization Status of Posted Writes to the ALM0 Register. WSYNCALM0
indicates if the effects of a posted write to ALM0 are visible to the CPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
Synchronization Status of Posted Writes to the CNT1 Register. WSYNCCNT1
indicates if the effects of a posted write to CNT1 are visible to the CPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
Synchronization Status of Posted Writes to the CNT0 Register. WSYNCCNT0
indicates if the effects of a posted write to CNT0 are visible to the CPU.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
Synchronization Status of Posted Clearances to Interrupt Sources in the SR0 Register.
WSYNCSR0 indicates if the effects of a posted write to SR0 are visible to the CPU. No
posting or associated masking is needed for clearances of the WPNDERRINT,
WSYNCINT, and WPENDINT bits in SR0, because these fields are sourced in the clock
domain of the core. Their clearance is immediate.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
Synchronization Status of Posted Writes to the CR0 Register. WSYNCCR0 indicates if
the effects of a posted write to CR0 are visible to the CPU.
0 Results of a posted write are not yet visible by the CPU.
1 Results of a posted write are visible by the CPU.
Write Pending Interrupt. WPENDINT is a sticky interrupt source that is activated
whenever there is room in the CPU to post a new write transaction to a 32 kHz
sourced MMR or MMR bit field in the RTC. To enable a WPENDINT interrupt, set
WPENDINTEN to 1 in the CR0 register. Cleared by writing a value of one to this bit.
0 There has been no change in the pending status of any posted write transaction in
the WUT since WPENDINT was last cleared.
1 A posted write transaction has been dispatched since WPENDINT was last cleared,
freeing up a slot for a new posted write by the CPU to the same MMR.
Write Synchronization Interrupt. WSYNCINT is a sticky interrupt source that is activated
whenever a posted write transaction to a 32 kHz sourced MMR or MMR bit field
completes and whose effects are then visible to the CPU. By checking the
synchronization status of posted write bits of SR0 (Bits[12:7]) and SR2 (Bits[15:14]),
the CPU can identify which posted write transaction has just completed and caused
the WSYNCINT interrupt source to stick (or restick if already active). Cleared by
writing 1 to this bit.
0 Since the CPU last cleared WSYNCINT, there has been no occurrence of the effects
of a posted write transaction to a 32 kHz sourced MMR or MMR bit field.
1 Since the CPU last cleared WSYNCINT, the effects of a posted write transaction to a
32 kHz sourced MMR or MMR bit field has become newly visible to the clock
domain of the CPU.
Write Pending Error Interrupt Source. This bit is a sticky interrupt source that indicates
that an error has occurred because the CPU attempted to write to a WUT register
while a previous write to the same register was pending execution. If multiple write
pending errors occur, WPNDERRINT sticks at the first occurrence. Cleared by writing
1 to this bit.
0 No posted write has been rejected by the WUT since WPNDERRINT was last cleared
by the CPU.
1 A posted write has been rejected by the WUT due to a previously posted write to
the same MMR, which is still awaiting execution. Such a rejection has occurred since
the CPU last cleared WPNDERRINT.
Rev. B | Page 293 of 312
UG-1262
Reset Access
0x1 R
0x1 R
0x1 R
0x1 R
0x1 R
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C