Count 0 Register; Count 1 Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual
Bits Bit Name Settings
7 WPNDCR0
[6:0] Reserved

COUNT 0 REGISTER

Address: 0x4000140C, Reset: 0x0000, Name: CNT0
CNT0 contains the lower 16 bits of the WUT counter, which maintains a real-time count in elapsed prescaled WUT time units. The
instantaneous value of CNT0 can be read back by the CPU. The CPU can also redefine the value in this register. In this case, the WUT
continues its real-time count from the redefined value.
Any write to CNT0 pends until a corresponding write to CNT1 is carried out by the CPU, so that the combined 32-bit count redefinition
can be executed as a single transaction. CNT0 and CNT1 can be written in any order, but paired twin writes must be carried out by the
CPU to have any effect on the WUT count. A paired write to CNT0 and CNT1 in any order zeroes the prescaler in the WUT and thus
causes a redefinition of elapsed time by the CPU to align exactly with newly created modulo 1 and modulo 60 boundaries. Such a
redefinition also causes the WUT to create a trim boundary and initiate a new trim interval. When the WUT count is redefined by the
CPU, no coincident trim adjustment of the count is carried out.
The WUT supports immediate redefinition of CNT0 and CNT1 while CR0, Bit 0 is active. Alternatively, the CPU can disable the WUT
by first making CR0, Bit 0 inactive while redefining these registers.
Table 383. Bit Descriptions for CNT0
Bits Bit Name Settings
[15:0] VALUE

COUNT 1 REGISTER

Address: 0x40001410, Reset: 0x0000, Name: CNT1
CNT1 contains the upper 16 bits of the WUT counter, which maintains a real-time count in elapsed prescaled WUT time units. Any
write to CNT1 pends until a corresponding write to CNT0 is carried out by the CPU, so that the combined 32-bit count redefinition can
be executed as a single transaction.
Table 384. Bit Descriptions for CNT1
Bits Bit Name Settings
[15:0] VALUE
Description
0 The WUT can accept new posted clearances of interrupt sources in SR0 located in
the 32 kHz domain.
1 A previously posted clearance of interrupt sources in SR0 and maintained in the
32 kHz domain is still awaiting execution. Additional clearances can still be
aggregated into the existing, pending transaction.
Pending Status of Posted Writes to CR0.
0 The WUT can accept a new posted write to CR0.
1 A previously posted write to CR0 is still awaiting execution. No new posting to this
MMR can be accepted.
Reserved.
Description
Lower 16 Prescaled Nonfractional Bits of the WUT Real-Time Count.
Description
Upper 16 Prescaled Nonfractional Bits of the WUT Real-Time Count.
Rev. B | Page 295 of 312
UG-1262
Reset Access
0x0 R
0x78 R
Reset Access
0x0 R/W
Reset Access
0x0 R/W