Configuration Registers - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

CONFIGURATION REGISTERS

Address: 0x40004010, Reset: 0x0000, Name: SPI0_CTL
Address: 0x40024010, Reset: 0x0000, Name: SPI1_CTL
Table 310. Bit Descriptions for SPI0_CTL, SPI1_CTL
Bits Bit Name Settings
15 Reserved
14 CSRST
13 TFLUSH
12 RFLUSH
11 CON
10 LOOPBACK
9 OEN
8 RXOF
7 ZEN
6 TIM
5 LSB
4 WOM
Description
Reserved.
Reset Mode for Chip Select Error Bit.
0 The bit counter continues from where it stopped. The SPI can receive the remaining bits
when the chip select is asserted and user code must ignore the SPIx_STAT, Bit 12 interrupt.
1 The bit counter is reset after a chip select error condition and the user code is expected
to clear SPIx_CTL, Bit 0. Set this bit for a recovery after a chip select error.
SPI Transmit FIFO Flush Enable.
0 Disable transmit FIFO flushing.
1 Flush the transmit FIFO. This bit does not clear itself and must be toggled if a single flush is
required. If this bit is left high, either the last transmitted value or 0x00 is transmitted
depending on the ZEN bit. Any writes to the transmit FIFO are ignored while this bit is set.
SPI Receive FIFO Flush Enable.
0 Disable receive FIFO flushing.
1 Flush the receive FIFO. This bit does not clear itself and must be toggled if a single flush
is required. If this bit is set, all incoming data is ignored and no interrupts are generated.
If set and the TIM bit = 0, a read of the receive FIFO initiates a transfer.
Continuous Transfer Enable.
Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid
0
data exists in the SPIx_TX register, a new transfer is initiated after a stall period of one
serial clock cycle.
1 Enable continuous transfer. In master mode, the transfer continues until no valid data is
available in the transmit FIFO. Chip select is asserted and remains asserted for the
duration of each 8-bit serial transfer until FIFO is empty.
Loopback Enable.
0 Normal mode.
1 Connect MISO to MOSI and test software.
Slave MISO Output Enable.
0 Disable the output driver on the MISO pin. The MISO pin is open circuit when this bit is clear.
1 MISO operates as normal.
SPI Receive Overflow Overwrite Enable.
0 The new serial byte received is discarded.
1 The valid data in the receive register is overwritten by the new serial byte received.
Transmit Zeros Enable.
0 Transmit the last transmitted value when there is no valid data in the transmit FIFO.
1 Transmit 0x00 when there is no valid data in the transmit FIFO.
SPI Transfer and Interrupt Mode.
0 Initiate transfer with a read of the SPIx_RX register. An interrupt only occurs when the
receive FIFO is full.
1 Initiate transfer with a write to the SPIx_TX register. An interrupt only occurs when the
transmit FIFO is empty.
LSB First Transfer Enable.
0 MSB transmitted first.
1 LSB transmitted first.
SPI Wire-OR'ed Mode.
0 Normal output levels.
1 Enables open circuit data output enable. External pull-up resistors required on data out pins.
ADuCM355
Rev. B | Page 250 of 312
Hardware Reference Manual
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W