Channel Bytes Swap Enable Set Register; Channel Bytes Swap Enable Clear Register; Channel Source Address Decrement Enable Set Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

CHANNEL BYTES SWAP ENABLE SET REGISTER

Address: 0x40010800, Reset: 0x00000000, Name: BS_SET
Table 213. Bit Descriptions for BS_SET
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN

CHANNEL BYTES SWAP ENABLE CLEAR REGISTER

Address: 0x40010804, Reset: 0x00000000, Name: BS_CLR
Table 214. Bit Descriptions for BS_CLR
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN

CHANNEL SOURCE ADDRESS DECREMENT ENABLE SET REGISTER

Address: 0x40010810, Reset: 0x00000000, Name: SRCADDR_SET
Table 215. Bit Descriptions for SRCADDR_SET
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN
Description
Reserved.
Byte Swap Status. This register is used to configure a DMA channel to use byte
swap. Each bit of the register represents the corresponding channel number in
the DMA controller. Bit 0 corresponds to DMA Channel 0. Bit M − 1 corresponds
to DMA Channel M – 1.
0 When read as 0, Channel C byte swap is disabled. When written as 0, no effect.
1 When read as 1, Channel C byte swap is enabled. When written as 1, byte swap
on Channel C is enabled.
Description
Reserved.
Disable Byte Swap. The BS_CLR write only register enables the user to configure a
DMA channel to not use byte swapping and use the default operation. Each bit of
the register represents the corresponding channel number in the DMA controller.
Bit 0 corresponds to DMA Channel 0. Bit M − 1 corresponds to DMA Channel M – 1.
0 No effect. Use the BS_SET register to enable byte swap on Channel C.
1 Disables byte swap on Channel C.
Description
Reserved.
Source Address Decrement Status and Configure Source Address Decrement.
The SRCADDR_SET register is used to configure the source address of a DMA
channel to decrement the address instead of incrementing the address after
each access. Each bit of the register represents the corresponding channel
number in the DMA controller. Bit 0 corresponds to DMA Channel 0. Bit M − 1
corresponds to DMA Channel M – 1.
0 When read as 0, Channel C source address decrement is disabled. When written
as 0, no effect. Use the SRCADDR_CLR register to disable source address
decrement on Channel C.
1 When read as 1, Channel C source address decrement is enabled. When written
as 1, source address decrement on Channel C is enabled.
ADuCM355
Rev. B | Page 182 of 312
Hardware Reference Manual
Reset
0x00
0x000000
Reset
0x00
0x000000
Reset
0x00
0x000000
Access
R
R/W
Access
R
W
Access
R
R/W