Clock Divider Configuration Register; Clock Gate Enable Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual

CLOCK DIVIDER CONFIGURATION REGISTER

Address: 0x400C0408, Reset: 0x0441, Name: CLKCON0
User must write CLKCON0KEY = 0xA815 before writing to CLKCON0.
Table 11. Bit Descriptions for CLKCON0
Bits Bit Name
[15:6] Reserved
[5:0] SYSCLKDIV

CLOCK GATE ENABLE REGISTER

Address: 0x400C0410, Reset: 0x010A, Name: CLKEN1
Table 12. Bit Descriptions for CLKEN1
Bits Bit Name Settings
[15:10] Reserved
9 AFECLKDIS
8 AFECLKSTA
7 GPT1DIS
6 GPT0DIS
5 ACLKDIS
4 Reserved
3 Reserved
2 Reserved
1 Reserved
0 Reserved
Settings Description
Reserved. Do not write to this bit.
System Clock Divider Configuration. The system clock divider is used to
provide a divided clock from the root clock, which drives the peripheral bus,
die to die interface, and most digital peripherals. System clock frequency
(f ) = root clock/SYSCLKDIV. Value range is from 1 to 32. Values larger than
SYS
32 are saturated to 32. Value 0 and Value 1 have the same results as divide
by 1. f must be ≤16 MHz. Characterization was completed only with
SYS
analog die system clock of 4 MHz, 8 MHz, and 16 MHz.
Description
Reserved.
AFE Die Clock Enable to AFE P2.2 Pad.
0 Connect AFE clock to AFE P2.2 pad.
1 Disconnect AFE clock from AFE P2.2 pad.
Reflects Status of CLKEN1 Bit, Read Only.
0 AFE clock connected to AFE die P2.2 pad.
1 AFE clock disconnected from AFE die P2.2 pad.
General-Purpose Timer 1 (GPT1) Clock Enable. This bit controls pulse width
modulation (PWM) Timer 1 clocks.
0 Turn on GTP1 clock.
1 Turn off GPT1 clock.
General-Purpose Timer 0 (GPT0) Clock Enable. This bit controls PWM Timer 0 clocks.
0 Turn on GPT0 clock.
1 Turn off GPT0 clock.
ACLK Clock Enable. This bit controls the clock to the DFT and the waveform
generator blocks control clock, including analog interface and digital signal
processing.
0 Turn on ACLK clock.
1 Turn off ACLK clock.
Reserved. Never write to this bit. Leave this bit cleared to 0.
Reserved. Never write to this bit.
Reserved. Never write to this bit. Leave this bit cleared to 0.
Reserved. Never write to this bit.
Reserved. Never write to this bit. Leave this bit cleared to 0.
Rev. B | Page 21 of 312
UG-1262
Reset Access
0x1 R/W
0x1 R/W
Reset Access
0x0 R
0x0 R/W
0x0 R
0x1 R/W
0x1 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W