Adc Calibration - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262
3. Configure the PGA gain setting as required. Write to ADCCON, Bits[18:16]. Setting these bits to 001 configures the PGA for a gain
of 1.5.
4. Configure the ADC update rate by writing to ADCFILTERCON. If the sinc2 filter is required, also write to AFECON, Bit 16.
5. Select the ADC positive and negative input channels by configuring ADCCON, Bits[12:0].
6. If ADC interrupts are required, enable the interrupts by setting the required ADC bits in the ADCINTIEN register. Enable the ADC
global interrupt to the Cortex-M3 core.

ADC CALIBRATION

Because of the multiple input types of the ADuCM355, there are multiple offset and gain calibration options. The ADC must be recalibrated
when switching from low power mode to high power mode, regardless of the gain change. For optimal performance, calibrate the ADC in
low power mode and high power mode, if both power modes are used. An error occurs in the high speed TIA offset and gain when
switching from low power to high power. Table 54 to Table 57 detail the registers associated with ADC voltage and gain calibration.
The current input channels (low power TIA0, low power TIA1, and high speed TIA) have an extra ADC calibration stage to that detailed
in Table 54. The extra stage is determined by the gain error introduced by each TIA gain resistor. When a current channel is selected by
the ADC, its calibration involves the use of a voltage measurement port relative to the PGA setting (as detailed in Table 54), and the
current selection relates to the TIA channel.
Example functions are provided with the
Table 54. Voltage Channel Offset and Gain Calibration Registers
PGA Gain Low Power Mode and High Power Mode Offset
Setting Registers
1 ADCOFFSETGN1
1.5 ADCOFFSETGN1P5
2 ADCOFFSETGN2
4 ADCOFFSETGN4
9 ADCOFFSETGN9
Table 55. Low Power TIA0 Channel Offset and Gain Calibration Registers
PGA Gain Setting
1
1.5
2
4
9
Table 56. Low Power TIA1 Channel Offset and Gain Calibration Registers, Low Power Mode Only
PGA Gain Setting
1
1.5
2
4
9
Table 57. High Speed TIA Channel Offset and Gain Calibration Registers
PGA Gain Setting
1
1.5
2
4
9
EVAL-ADuCM355QSPZ
Offset Registers
ADCOFFSETGN1, ADCOFFSETLPTIA0
ADCOFFSETGN1P5, ADCOFFSETLPTIA0
ADCOFFSETGN2, ADCOFFSETLPTIA0
ADCOFFSETGN4, ADCOFFSETLPTIA0
ADCOFFSETGN9, ADCOFFSETLPTIA0
Offset Registers
ADCOFFSETGN1, ADCOFFSETLPTIA1
ADCOFFSETGN1P5, ADCOFFSETLPTIA1
ADCOFFSETGN2, ADCOFFSETLPTIA1
ADCOFFSETGN4, ADCOFFSETLPTIA1
ADCOFFSETGN9, ADCOFFSETLPTIA1
Offset Registers
ADCOFFSETGN1, ADCOFFSETHSTIA
ADCOFFSETGN1P5, ADCOFFSETHSTIA
ADCOFFSETGN2, ADCOFFSETHSTIA
ADCOFFSETGN4, ADCOFFSETHSTIA
ADCOFFSETGN9, ADCOFFSETHSTIA
ADuCM355
to demonstrate how to calibrate the ADC.
Low Power Mode and High Power Mode Gain
Registers
ADCGAINGN1
ADCGAINGN1P5
ADCGAINGN2
ADCGAINGN4
ADCGAINGN9
Rev. B | Page 64 of 312
Hardware Reference Manual
Gain Registers
ADCGAINGN1, ADCGNLPTIA0
ADCGAINGN1P5, ADCGNLPTIA0
ADCGAINGN2, ADCGNLPTIA0
ADCGAINGN4, ADCGNLPTIA0
ADCGAINGN9, ADCGNLPTIA0
Gain Registers
ADCGAINGN1, ADCGNLPTIA1
ADCGAINGN1P5, ADCGNLPTIA1
ADCGAINGN2, ADCGNLPTIA1
ADCGAINGN4, ADCGNLPTIA1
ADCGAINGN9, ADCGNLPTIA1
Gain Registers
ADCGAINGN1, ADCGNHSTIA
ADCGAINGN1P5, ADCGNHSTIA
ADCGAINGN2, ADCGNHSTIA
ADCGAINGN4, ADCGNHSTIA
ADCGAINGN9, ADCGNHSTIA