Analog Devices ADuCM355 Hardware Reference Manual page 141

ADuCM355 Hardware Reference Manual
Interrupt Controller Select Registers
Address 0x400C3008, Reset: 0x00002000, Name: INTCSEL0
Address 0x400C300C, Reset: 0x00002000, Name: INTCSEL1
Table 177. Bit Descriptions for INTCSEL0 and INTCSEL1 Registers
Bits Bit Name
31 INTSEL31
30 Reserved
29 INTSEL29
28 Reserved
27 INTSEL27
26 INTSEL26
25 INTSEL25
24 INTSEL24
23 INTSEL23
[22:18] Reserved
17 INTSEL17
16 INTSEL16
15 INTSEL15
14 Reserved
13 INTSEL13
12 INTSEL12
11 INTSEL11
10 INTSEL10
Settings Description
Attempt to Break IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Reserved.
Outlier IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Reserved.
Data FIFO Underflow IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Data FIFO Overflow IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Data FIFO Threshold IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Data FIFO Empty IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Data FIFO Full IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Reserved.
Sequencer Timeout Error IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Sequencer Timeout Finished IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
End of Sequence IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Reserved.
Bootloader Done IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Custom Interrupt 3 Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Custom Interrupt 2 Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Custom Interrupt 1 Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Rev. B | Page 141 of 312
UG-1262
Reset Access
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x1 R/W
0x0 R/W
0x0 R/W
0x0 R/W