Analog Devices ADuCM355 Hardware Reference Manual page 142

UG-1262
Bits Bit Name
9 INTSEL9
8 Reserved
7 INTSEL7
6 INTSEL6
5 INTSEL5
4 INTSEL4
3 INTSEL3
2 INTSEL2
1 INTSEL1
0 INTSEL0
Interrupt Controller Flag Registers
Address 0x400C3010, Reset: 0x00000000, Name: INTCFLAG0
Address 0x400C3014, Reset: 0x00000000, Name: INTCFLAG1
Table 178. Bit Descriptions for INTCFLAG0 and INTCFLAG1 Registers
Bits Bit Name Settings
31 FLAG31
30 Reserved
29 FLAG29
28 Reserved
27 FLAG27
26 FLAG26
Settings Description
Custom Interrupt 0 Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Reserved.
Mean IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
ADC Delta Fail IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
ADC Maximum Fail IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
ADC Minimum Fail IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Temperature Result IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Sinc2 Filter Result Ready IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
DFT Result IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
ADC Result IRQ Enable.
0 Interrupt disabled.
1 Interrupt enabled.
Description
Attempt to Break IRQ Status. This bit is set if a Sequence B request arrives when
Sequence A is running, indicating that Sequence B is ignored.
0 Interrupt not asserted.
1 Interrupt asserted.
Reserved.
Outlier IRQ Status.
0 Interrupt not asserted.
1 Interrupt asserted.
Reserved.
Data FIFO Underflow IRQ Status.
0 Interrupt not asserted.
1 Interrupt asserted.
Data FIFO Overflow IRQ Status.
0 Interrupt not asserted.
1 Interrupt asserted.
ADuCM355
Rev. B | Page 142 of 312
Hardware Reference Manual
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R