Analog Devices ADuCM355 Hardware Reference Manual page 172

UG-1262
Table 195. CHNL_CFG for Primary Data Structure in Peripheral Scatter Gather Mode, CHNL_CFG, Bits[2:0] = 110
Bit(s) Name
[31:30] DST_INC
[29:28] Reserved
[27:26] SRC_INC
[25:24] SRC_SIZE
[23:18] Reserved
[17:14] R_POWER
[13:4] N_MINUS_1
3 Reserved
[2:0] CYCLE_CTRL
Description
Set to 10, configures the controller to use word increments for the address.
Undefined. Write as 0.
Set to 10, configures the controller to use word increments for the address.
Set to 10, configures the controller to use word transfers.
Undefined. Write as 0.
Set to 0010, indicates that the DMA controller performed four transfers without rearbitration.
Configures the controller to perform N DMA transfers, where N is a multiple of four.
Undefined. Write as 0.
Set to 110, configures the controller to perform a peripheral scatter gather DMA cycle.
PRIMARY
COPY FROM A
REQUEST
IN MEMORY TO
ALTERNATE
REQUESTS
COPY FROM B
IN MEMORY TO
ALTERNATE
REQUESTS
REQUESTS
COPY FROM C
IN MEMORY TO
ALTERNATE
REQUESTS
COPY FROM D
IN MEMORY TO
ALTERNATE
NOTES
1. FOR ALL PRIMARY TO ALTERNATE TRANSITIONS, THE CONTROLLER
DOES NOT ENTER THE ARBITRATION PROCESS AND IMMEDIATELY
PERFORMS THE DMA TRANSFER THAT THE ALTERNATE CHANNEL
CONTROL DATA STRUCTURE SPECIFIES.
Figure 47. Peripheral Scatter Gather DMA Transfer
Rev. B | Page 172 of 312
ADuCM355 Hardware Reference Manual
ALTERNATE
TASK A
R
N = 3, 2 = 4
TASK B
R
N = 8, 2 = 2
TASK C
R
N = 5, 2 = 8
TASK D
R
N = 4, 2 = 4
DMA_DONE[C]