Master And Slave Shared Control Register; Automatic Stretch Control For Master And Slave Mode Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual
Bits Bit Name Settings
[3:2] SRXF
[1:0] STXF

MASTER AND SLAVE SHARED CONTROL REGISTER

Address: 0x40003050, Reset: 0x0000, Name: SHCTL
Table 302. Bit Descriptions for SHCTL
Bits Bit Name Settings
[15:1] Reserved
0 RST

AUTOMATIC STRETCH CONTROL FOR MASTER AND SLAVE MODE REGISTER

Address: 0x40003058, Reset: 0x0000, Name: ASTRETCH_SCL
Table 303. Bit Descriptions for ASTRETCH_SCL
Bits Bit Name Settings
[15:10] Reserved
9 SLVTMO
8 MSTTMO
[7:4] SLV
0000
0001 to
1110
1111
Description
Slave Receive FIFO Status. The status is a count of the number of bytes in a FIFO.
00 FIFO empty.
01 1 bytes in the FIFO.
10 2 bytes in the FIFO.
11 Reserved.
Slave Transmit FIFO Status. The status is a count of the number of bytes in a FIFO.
00 FIFO empty.
01 1 byte in the FIFO.
10 2 bytes in the FIFO.
11 Reserved.
Description
Reserved.
Reset LINEBUSY. Setting this bit resets the LINEBUSY status bit (Bit 10 in the
MSTAT register).
0 No effect.
2
1 Reset the I C start and stop detection circuits.
Description
Reserved.
Stretch Timeout Status Bit for Slave.
0 Cleared when this bit is read.
1 Set when slave automatic stretch mode has timed out.
Stretch Timeout Status Bit for Master.
0 Cleared when this bit is read.
1 Set when master automatic stretch mode has timed out.
Automatic Stretch Mode Control for Slave. These bits control automatic stretch mode for
slave operation. These bits allow the slave to hold the I2C_SCL line low and gain more
time to service an interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a
bus lockup condition where the slave indefinitely holds I2C_SCL low. As a slave
transmitter, I2C_SCL is automatically stretched from the negative edge of I2C_SCL (if the
slave transmit FIFO is empty) before sending an acknowledge or a no acknowledge for an
address byte, or before sending data for a data byte. Stretching stops when the slave
transmit FIFO is no longer empty or a timeout occurs. As a slave receiver, the I2C_SCL
clock is automatically stretched from the negative edge of I2C_SCL before sending an
acknowledge or a no acknowledge when the slave receive FIFO is full. Stretching stops
when the slave receive FIFO is no longer in an overflow condition or a timeout occurs.
Automatic slave clock stretching disabled.
Automatic slave clock stretching enabled. The timeout period is defined as follows:

DIV[15 : 8] ( DIV[7 : 4]
UCLK CTL1[13 : 8] CTL1[13 : 8] /
Note that the I 2 C bus baud rate has no influence on the slave stretch timeout period.
Automatic slave clock stretching enabled with indefinite timeout period.


1)

ASTRETCH SCL[7 :4] _
2

Rev. B | Page 239 of 312

UG-1262
Reset Access
0x0 R
0x0 R
Reset Access
0x0000 R/W
0x0 W
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R/W