System Exceptions And Peripheral Interrupts; Cortex-M3 And Fault Management - Analog Devices ADuCM355 Hardware Reference Manual

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SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

The ADuCM355 integrates an Arm Cortex-M3 processor, which supports several system exceptions and interrupts generated by
peripherals. Table 40 lists the Arm Cortex-M3 processor system exceptions.
Table 40. System Exceptions
Exception
Number Type
1 Reset
2 NMI
3 Hard fault
4 Memory
management fault
5 Bus fault
6 Usage fault
7 to 10 Reserved
11 SVCALL
12 Debug monitor
13 Reserved
14 PENDSV
15 SYSTICK
The NVIC controls the peripheral interrupts, which are listed in Table 41. All interrupt sources can wake up the Arm Cortex-M3 core
from flexi mode. Only a limited number of interrupts can wake up the processor from hibernate mode, as shown in Table 41. When the
device is woken up from flexi or hibernate mode, it returns to active mode. If the processor enters flexi or hibernate mode while the
processor is in an interrupt handler, only an interrupt source with a higher priority than the current interrupt can wake up the device.
Higher priority means having a higher value in a bit setting in the Cortex IPRx registers.
Two steps are usually required to configure an interrupt as follows:
1. Configure a peripheral to generate an interrupt request to the NVIC.
2. Configure the NVIC for that peripheral request.
Table 41. Interrupt Vectors
Exception Number IRQx
16 IRQ0
17 IRQ1
18 IRQ2
19 IRQ3
20 IRQ4
21 IRQ5
22 IRQ6
23 IRQ7
24 IRQ8
25 IRQ9
26 IRQ10
27 IRQ11
28 IRQ12
29 IRQ13
30 IRQ14
31 IRQ15
Priority Description
−3 (highest) Any reset.
−2 Nonmaskable interrupt connected to a combination of logical ORs of
DVDD_REG pin undervoltage or AVDD_DD pin undervoltage. See Table 23.
−1 All fault conditions if the corresponding fault handler is not enabled.
Programmable Access to invalid locations.
Programmable Prefetch fault, memory access fault, data abort, and other address or memory
related faults.
Programmable Same as undefined instruction executed or invalid state transition attempt.
Not applicable Reserved.
Programmable System service call with supervisor mode call (SVC) instruction. Used for system
function calls.
Programmable Debug monitor for breakpoint, watchpoint, or external debug requests.
Not applicable Reserved.
Programmable Pendable request for system service. Used for queuing system calls until other
tasks and interrupts are serviced.
Programmable System tick timer.
Vector
Digital Die Real-Time Clock 1, wake-up timer, hibernate RTC
Reserved
External Interrupt 1 (SYS_WAKE)
Reserved
External Interrupt 3, UART receive wake-up interrupt, and INTCxxx
register interrupt
Reserved
Digital Die DVDD_REG pin overrange
DVDD pin voltage range
Reserved
GPIO Interrupt A
GPIO Interrupt B
Digital Die General-Purpose Timer 0
Digital Die General-Purpose Timer 1
Flash controller
UART0
SPI0
Rev. B | Page 42 of 312
ADuCM355 Hardware Reference Manual
Wake Up From
Flexi Hibernate
Yes Yes
Not applicable Not applicable
Yes Yes
Not applicable Not applicable
Yes Yes
Yes No
Yes No
Yes Yes
Not applicable Not applicable
Yes No
Yes No
Yes No
Yes No
Yes No
Yes No
1
Yes No