Number Of Repeat Adc Conversions Register; Buffer Configuration Register; Calibration Lock Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262
Bits Bit Name
1 V1P8HPADCILIMITEN
0 V1P8HPADCEN

NUMBER OF REPEAT ADC CONVERSIONS REGISTER

Address: 0x400C21F0, Reset: 0x00000160, Name: REPEATADCCNV
Table 75. Bit Descriptions for REPEATADCCNV
Bits Bit Name Settings
[31:5] Reserved
[4] NUM
[3:1] Reserved
0 EN

BUFFER CONFIGURATION REGISTER

Address: 0x400C238C, Reset: 0x005F3D00, Name: ADCBUFCON
The recommended value for this register is 0x005F3D0F in high power mode and 0x005F3D04 in low power mode.
Table 76. Bit Descriptions for ADCBUFCON
Bits Bit Name
[31:4] Reserved
3 CHOPDIS
2 CHOPDIS
1 CHOPDIS
0

CALIBRATION LOCK REGISTER

Address: 0x400C2230, Reset: 0x00000000, Name: CALDATLOCK
Table 77. Bit Descriptions for CALDATLOCK
Bits Bit Name Settings
[31:0] KEY
Settings Description
High Power ADC Input Current Limit. Protects ADC input buffer.
0 Disable buffer current limit.
1 Enable buffer current limit. Recommended setting.
High Power 1.8 V Reference Buffer. Enable for normal ADC conversions.
0 Disable 1.8 V high power ADC reference buffer.
1 Enable 1.8 V high power ADC reference buffer.
Description
Reserved.
Write 1 to this bit to enable single or continuous conversion.
Reserved.
Enable Repeat ADC Conversions.
0 Disable repeat ADC conversions.
1 Enable repeat ADC conversions.
Settings Description
Reserved.
Configure Offset Cancellation Buffer Chop.
0 Enable chop.
1 Disable chop.
Configure ADC Buffer Chop.
0 Enable chop.
1 Disable chop.
Configure PGA Chop.
0 Enable chop.
1 Disable chop.
Configure Front-End Buffer Chop.
0 Enable chop.
1 Disable chop.
Description
Password for Calibration Data Registers. Prevents overwriting of data
after the calibration phase.
0xDE87A5AF Calibration data registers read/write.
ADuCM355
Rev. B | Page 76 of 312
Hardware Reference Manual
Reset
0x00016
0x0
0x0
0x0
Reset
0x0
0x0
0x0
0x0
Reset Access
0x1 R/W
0x1 R/W
Access
R
R
R
R/W
Access
R
R/W
R/W
R/W
Reset Access
0x0 R/W