Analog Devices ADuCM355 Hardware Reference Manual page 216

UG-1262
Interrupt bits are cleared by writing 1 to the appropriate bit location in GPxINT. Writing 0 has no effect. If interrupts are enabled to the
core (GPxIENA, GPxIENB), an interrupt GPxINT value of 1 results in an interrupt to the core. Clear this GPxINT bit during servicing of
the interrupt. When GPxINT is read as 0, a rising or falling edge is not detected on the corresponding GPIO pin since this bit was last
cleared. When read as 1, a rising or falling edge (GPxPOL selectable) is detected on the corresponding GPIO pin. This bit can be software
cleared by writing 1 to the appropriate GPxINT bit.
The following is example code to enable BM/P1.1 as an input interrupt:
pADI_GPIO1->PE = 0x2;
pADI_GPIO1->IEN = 0x1;
pADI_GPIO1->IENA = 0x2;
pADI_GPIO1->POL = 0x0;
NVIC_EnableIRQ(SYS_GPIO_INTA_IRQn);
The following is example code for the GPIO pin interrupt handler routine:
void GPIO_A_Int_Handler()
{
unsigned int uiIntSta = 0;
uiIntSta = pADI_GPIO1->INT;
if ((uiIntSta & 0x2) ==0x2)
{
pADI_GPIO1->INT |= 0x2;
}
}
The following is example code to set P0.3/SPI0_ CS as an output. Write to GP0OUT, GP0SET, GP0CLR, and GP0TGL to set the level on
P0.3/SPI0_ CS :
pADI_GPIO0->OEN |= 0x8;
ADuCM355
// Enable internal pull-up resistors on P1.1
// Enable P1.1 input path
// Enable External Interrupt A on P1.11
// Interrupt on falling edge
// Enable GPIO_INTA interrupt source in NVIC
// interrupt expected on P1.1
// Configure P0.3 as an output
Rev. B | Page 216 of 312
Hardware Reference Manual