Control Data Configuration - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

CONTROL DATA CONFIGURATION

For each DMA transfer, the CHNL_CFG memory location provides the control information for the DMA transfer to the controller.
Table 193. CHNL_CFG Control Data Configuration
Source
Bit(s) Name Data Width
[31:30] DST_INC
Byte
Half word
Word
[29:28] Reserved
[27:26] SRC_INC
Byte
Half word
Word
[25:24] SRC_SIZE
[23:18] Reserved
Setting Description
Destination Address Increment. The address increment depends on the source data width.
00 Source address increment is byte.
01 Source address increment is half word.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the DST_END_PTR memory
location.
00 Reserved.
01 Source address increment is half word.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the DST_END_PTR memory
location.
00 Reserved.
01 Reserved.
10 Source address increment is word.
No increment. Address remains set to the value contained in the DST_END_PTR memory
11
location.
Undefined. Write as zero.
Source Address Increment. The address increment depends on the source data width.
00 Source address increment is byte.
01 Source address increment is half word.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the SRC_END_PTR memory
location.
00 Reserved.
01 Source address increment is half word.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the SRC_END_PTR memory
location.
00 Reserved.
01 Reserved.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the SRC_END_PTR memory
location.
Size of the Source Data.
00 Byte.
01 Half word.
10 Word.
11 Reserved.
Undefined. Write as 0.
Rev. B | Page 166 of 312
ADuCM355 Hardware Reference Manual