Slave Receive Register; Slave Transmit Register; Hardware General Call Id Register; First Slave Address Device Id Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual
Bits Bit Name Settings
2 STXREQ
1 STXUR
0 STXFSEREQ

SLAVE RECEIVE REGISTER

Address: 0x40003030, Reset: 0x0000, Name: SRX
Table 294. Bit Descriptions for SRX
Bits Bit Name
[15:8] Reserved
[7:0] SRX

SLAVE TRANSMIT REGISTER

Address: 0x40003034, Reset: 0x0000, Name: STX
Table 295. Bit Descriptions for STX
Bits Bit Name
[15:8] Reserved
[7:0] ISTX

HARDWARE GENERAL CALL ID REGISTER

Address: 0x40003038, Reset: 0x0000, Name: ALT
Table 296. Bit Descriptions for ALT
Bits Bit Name Settings
[15:8] Reserved
[7:0] ALT

FIRST SLAVE ADDRESS DEVICE ID REGISTER

Address: 0x4000303C, Reset: 0x0000, Name: ID0
Table 297. Bit Descriptions for ID0
Bits Bit Name Settings
[15:8] Reserved
[7:0] ID0
Description
Slave Transmit Request. If SCTL, Bit 5 = 0, this bit is set when the direction bit for a
transfer is received high. As long as the transmit FIFO is not full, this bit remains
asserted. Initially, this bit is asserted on the negative edge of the SCL pulse that
clocks in the direction bit (if the device address matches). If SCTL, Bit 5 = 1, this bit is
set when the direction bit for a transfer is received high. As long as the transmit FIFO
is not full, this bit remains asserted. Initially, this bit is asserted after the positive edge
of the I2C_SCL pulse that clocks in the direction bit (if the device address matches).
This bit is cleared on a read of the SSTAT register.
Slave Transmit FIFO Underflow. This bit is set if a master requests data from the
device, and the transmit FIFO is empty for the rising edge of SCL.
Slave Transmit FIFO Status or Early Request. If SCTL, Bit 5 = 0, this bit is asserted
whenever the slave transmit FIFO is empty. If SCTL, Bit 5 = 1, this bit is set when the
direction bit for a transfer is received high. This bit asserts on the positive edge of the
I2C_SCL clock pulse that clocks in the direction bit if the device address matches. This
bit only asserts once for a transfer and is cleared when read if SCTL, Bit 5 is asserted.
Settings Description
Reserved.
Slave Receive Register.
Settings Description
Reserved.
Slave Transmit Register.
Description
Reserved.
Slave Alternative. This register is used in conjunction with SCTL, Bit 3 to match a master
generating a hardware general call. This register is used when a master device cannot
be programmed with the address of a slave, and instead the slave must recognize the
address of the master.
Description
Reserved.
Slave Device ID 0. ID0, Bits[7:1] are programmed with the device ID. ID0, Bit 0 is don't care.
See SCTL, Bit 1 to see how this register is programmed with a 10-bit address. Take care to
2
avoid I C reserved slave addresses with values less than 0x10 and greater than 0xF6.
Rev. B | Page 237 of 312
UG-1262
Reset Access
0x0 RC
0x0 RC
0x1 R/W
Reset Access
0x0 R
0x0 R
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W