Averaging, Statistics, And Outlier Detection Options - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual
When changing ADC input channels, restarting the ADC, or changing the ADC update rates via the ADCFILTERCON register, reset the
sinc2 filter. If the sinc2 filter is not reset, the ADC samples with the new settings are inaccurate.
The following are example instructions:
pADI_AFE->AFECON &= (~(BITM_AFE_AFECON_SINC2EN)); // Clear AFECON[16]
pADI_AFE->AFECON |= BITM_AFE_AFECON_SINC2EN; // Set AFECON[16]
Power Supply Rejection Filter (50 Hz or 60 Hz Mains Filter)
To enable the 50 Hz or 60 Hz notch filter for filtering mains noise, clear ADCFILTERCON, Bit 4 = 0 and set AFECON, Bit 16 = 1. The
input is the sinc2 filter output. The input rate is dependent on the sinc3 and sinc2 settings. If selected, the power supply rejection filter
output can be read via the SINC2DAT register. Table 53 describes the digital filter settings that support simultaneous 50 Hz or 60 Hz
mains rejection.
Table 53. Digital Filter Settings for 50 Hz or 60 Hz Mains Rejection
ADCFILTERCON Power Mode
Bits[13:8] Value (PMBW Bit 0)
0b000011 0 (low power
mode)
0b100111 0 (low power
mode)
0b101011 0 (low power
mode)
0b101011 1 (high power
mode)
Gain Correction
The gain correction of the sinc2 filter and power supply rejection filter occurs in the gain correction block. The block is automatically
enabled in hardware, and no user configuration is required.
Digital DFT
The DFT accelerator is intended for use during impedance measurements. To enable the DFT block, set AFECON, Bit 15 = 1. The input can be
the raw ADC results, sinc2 output, sinc3 output (ADCDAT register), or the power supply filter output (SINC2DAT register).
Configure the DFT using DFTCON, Bits[21:20]. The DFT outputs a complex number (real and imaginary terms) that represents the
overall DFT result for the selected number of ADC samples of the applied ac waveform. See the DFT Result, Real Part Register section
and the DFT Result, Imaginary Part Register section. The number of samples used by the DFT is configurable via DFTCON, Bits[7:4]
(see the AFE DSP Configuration Register section). A Hanning window (raised cosine window) option is available. To enable the
Hanning window, set DFTCON, Bit 0 to 1. If enabled, values outside the selected interval are set to 0. It is recommended to enable the
Hanning window.

AVERAGING, STATISTICS, AND OUTLIER DETECTION OPTIONS

Averaging Option
The ADuCM355 supports averaging of the sinc3 output. The number of samples to average is configured via ADCFILTERCON, Bits[15:14].
Statistics Option
The ADuCM355 supports the calculation of the mean value for a programmable sample size of the sinc3 output. This calculation is
controlled by the STATSCON register. The number of samples used for statistics is configured via STATSCON, Bits[6:4].
Outlier Detection Options
The ADuCM355 provides outlier detection. Use the ADCMIN and ADCMAX registers to trigger an interrupt if the ADCDAT result
from the ADC is outside the limits of the value in the ADCMIN and ADCMAX registers.
The hysteresis values are also programmable. For more details, see the Minimum Value Check Register section, the Maximum Value
Check Register section, and the Delta Check Register section.
ADC Clock Sinc3
Setting Oversampling
(MHz) Setting
16 5
16 2
16 2
32 2
Rev. B | Page 61 of 312
Sinc2 Final ADC Output Update
Oversampling Rate in Samples per
Setting Second
178 900
667 600
1333 300
1333 600
UG-1262
Filter Settling
Time (ms)
37
37
37
37