Analog Devices ADuCM355 Hardware Reference Manual page 240

UG-1262
Bits Bit Name Settings
[3:0] MST
0000
0001 to
1110
1111
Description
Automatic Stretch Mode Control for Master. These bits control automatic stretch
mode for master operation. These bits allow the master to hold the I2C_SCL line low
and gain more time to service an interrupt, load a FIFO, or read a FIFO. Use the
timeout feature to avoid a bus lockup condition where the master indefinitely holds
I2C_SCL low. As a master transmitter, I2C_SCL is automatically stretched from the
negative edge of I2C_SCL (if the master transmit FIFO is empty) before sending an
acknowledge or a no acknowledge for an address byte, or before sending data for a
data byte. Stretching stops when the master transmit FIFO is no longer empty or a
timeout occurs. As a master receiver, the I2C_SCL clock is automatically stretched
from the negative edge of I2C_SCL before sending an acknowledge or a no
acknowledge when the master receive FIFO is full. Stretching stops when the master
receive FIFO is no longer in an overflow condition or a timeout occurs.
Automatic master clock stretching disabled.
Automatic master clock stretching enabled. The timeout period is defined as follows:

DIV[15 : 8] ( DIV[7 : 4]

UCLK CTL1[13 : 8] CTL1[13 : 8] /
Automatic master clock stretching enabled with indefinite timeout period.
Rev. B | Page 240 of 312
ADuCM355 Hardware Reference Manual
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 
1)

ASTRETCH SCL[3:0] _
2
Reset Access
0x0 R/W