Interrupt Sources From The Analog Die - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262 ADuCM355 Hardware Reference Manual
Internal to the Arm Cortex-M3 processor, the highest user-programmable priority (0) is treated as fourth priority after a reset, an NMI,
or a hard fault. The ADuCM355 implements three priority bits, which means that eight priority levels are available as programmable
priorities. 0 is the default for all the programmable priorities. If the same priority level is assigned to two or more interrupts, their
hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both
Digital Die General-Purpose Timer 0 and Digital Die General-Purpose Timer 1 are priority Level 1, Digital Die General-Purpose Timer 0
has higher priority.
To enable an interrupt for any peripheral from IRQ0 to IRQ31, set the appropriate bit in the Cortex ISER0 register. ISER0 is a 32-bit
register, and each bit corresponds to the first 32 entries in Table 41.
For example, to enable the External Interrupt 0 interrupt source in the NVIC, set ISER0, Bit 2 = 1. Similarly, to disable External Interrupt 1,
SYS_WAKE, set ICER0, Bit 2 = 1.
To enable an interrupt for any peripheral from IRQ32 to IRQ63, set the appropriate bit in the Cortex ISER1 register. ISER1 is a 32-bit
register, and Bit 0 to Bit 31 in the ISER1 register correspond to IRQ32 to IRQ63.
For example, to enable the General-Purpose Timer 2 interrupt source in the NVIC, set ISER1, Bit 8 = 1. Similarly, to disable the General-
Purpose Timer 2 interrupt, set ICER1, Bit 8 = 1.
Alternatively, CMSIS provides a number of useful NVIC functions in the core_cm3.h file. The NVIC_EnableIRQ (TMR2_EVT_IRQn)
function enables the General-Purpose Timer 2 interrupt. The interrupt can be disabled by calling the NVIC_DisableIRQ (TMR2_EVT_IRQn)
function.
To set the priority of a peripheral interrupt, set the Cortex IPRx registers appropriately or call the NVIC_SetPriority() function. For
example, NVIC_SetPriority (TMR2_EVT_IRQn, 2) configures the General-Purpose Timer 2 interrupt with a priority level of 2.
Table 43 lists the registers to enable and disable relevant interrupts and set the priority levels. The registers in Table 43 are defined in the
CMSIS core_cm3.h file, which is provided with tools from third party vendors.

INTERRUPT SOURCES FROM THE ANALOG DIE

DIGITAL DIE
CORTEX-M3 + NVIC
IRQ48 TO IRQ57
DIE TO DIE
INTERFACE
IRQs
ANALOG
DIE
Figure 5. Analog Die Interrupt Connections to Digital Die
The analog die peripherals provide different interrupt sources to the NVIC. These sources can be selected via the standard internal die to
die interface. The analog die interrupts connect to NVIC IRQ48 to IRQ57, as shown in Figure 5. Table 42 lists all the analog die interrupt sources
(interrupt enable register bit and interrupt status bit) for IRQ48, Exception Number 64, via the interrupt enable register, ADCINTIEN.
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