Uart Control Register; Receive Fifo Count Register; Transmit Fifo Count Register; Rs485 Half-Duplex Control Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual

UART CONTROL REGISTER

Address: 0x40005030, Reset: 0x0100, Name: COMCTL
Table 334. Bit Descriptions for COMCTL
Bits Bit Name
[15:8] REV
[7:5] Reserved
4 RXINV
[3:2] Reserved
1 FORCECLKON
0 Reserved

RECEIVE FIFO COUNT REGISTER

Address: 0x40005034, Reset: 0x0000, Name: COMRFC
Table 335. Bit Descriptions for COMRFC
Bits Bit Name
[15:5] Reserved
[4:0] RFC

TRANSMIT FIFO COUNT REGISTER

Address: 0x40005038, Reset: 0x0000, Name: COMTFC
Table 336. Bit Descriptions for COMTFC
Bits Bit Name
[15:5] Reserved
[4:0] TFC

RS485 HALF-DUPLEX CONTROL REGISTER

Address: 0x4000503C, Reset: 0x0000, Name: COMRSC
Table 337. Bit Descriptions for COMRSC
Bits Bit Name Settings
[15:4] Reserved
3 DISTX
2 DISRX
1 OENSP
0 OENP
Settings Description
UART Revision ID.
Reserved.
Invert Receiver Line.
0 Do not invert receiver line (idling high).
1 Invert receiver line (idling low).
Reserved.
Force PCLK to UART On All the Time.
0 PCLK to UART automatically clock gated.
1 PCLK to UART always on.
Reserved.
Settings Description
Reserved.
Current Receive FIFO Data Bytes.
Settings Description
Reserved.
Current Transmit FIFO Data Bytes.
Description
Reserved.
Disable Transmit when Receiving.
Disable Receive when Transmitting.
UART_SOUT Deassert Before Full Stop Bits.
0 UART_SOUT deasserts at same time as full stop bits.
1 UART_SOUT deasserts half bit earlier than full stop bits.
UART_SOUT Polarity.
0 High active.
1 Low active.
Rev. B | Page 265 of 312
UG-1262
Reset Access
0x1 R
0x0 R
0x0 R/W
0x0 R
0x0 R/W
0x0 R
Reset Access
0x0 R
0x0 R
Reset Access
0x0 R
0x0 R
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W