Interrupt Enable Register; 16-Bit Load Value Register; 16-Bit Timer Value Register; Control Register - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual

INTERRUPT ENABLE REGISTER

Address: 0x400C0D28, Reset: 0x0000, Name: INTEN
Table 362. Bit Descriptions for INTEN
Bits Bit Name Settings
[15:1] Reserved
0 INTEN

16-BIT LOAD VALUE REGISTER

Address: 0x400C0E00, Reset: 0x0000, Name: LOAD
Table 363. Bit Descriptions for LOAD
Bits Bit Name Settings
[15:0] VALUE

16-BIT TIMER VALUE REGISTER

Address: 0x400C0E04, Reset: 0x0000, Name: CURCNT
Table 364. Bit Descriptions for CURCNT
Bits Bit Name Settings
[15:0] VALUE

CONTROL REGISTER

Address: 0x400C0E08, Reset: 0x000A, Name: CTL
Table 365. Bit Descriptions for CTL
Bits Bit Name Settings
15 SYNCBYP
14 RSTEN
13 EVTEN
[12:8] EVTRANGE
7 RLD
Description
Reserved.
Interrupt Enable. This value is used when the PWM is operating in match mode. The
PWM output is asserted when the up or down counter is equal to this match value.
PWM output is deasserted again when a timeout event occurs. If the match value is never
reached, or occurs simultaneous to a timeout event, the PWM output remains idle.
Description
Load Value. The up or down counter is periodically loaded with this value if periodic
mode is selected (CTL, Bit 3 = 1). Writes from this bit during up or down counter
timeout events are delayed until the event has passed.
Description
Current Count. Reflects the current up or down counter value. Value delayed two PCLK
cycles due to clock synchronizers.
Description
Synchronization Bypass. Used to bypass the synchronization logic within the block.
Use only with synchronous clocks. This bit field also changes the PRE bit maximum
prescaler count from 3 to 0.
Counter and Prescale Reset Enable. Used to enable and disable the reset feature. Used
in conjunction with CTL, Bit 13 (EVTEN) and CTL, Bits[12:8] (EVTRANGE). When a
selected event occurs, the 16-bit counter and 8-bit prescale are reset. This reset is
required in PWM demodulation mode.
Event Select. Used to enable and disable the capture of events. Used in conjunction
with the CTL, Bits[12:8] (EVTRANGE) bits. When a selected event occurs, the current
value of the up or down counter is captured in GPTx_CAPTURE.
0 Events are not captured.
1 Events are captured.
Event Select Range. Timer event select range (0 to 31).
Reload Control. This bit is only used for periodic mode. This bit allows the user to
select whether the up or down counter is reset only on a timeout event or also when
CLRINT, Bit 0 is set.
1 Resets the up or down counter when the clear timeout interrupt bit is set.
0 Up or down counter is only reset on a timeout event.
Rev. B | Page 279 of 312
UG-1262
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R/W
Reset Access
0x0 R
Reset Access
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W