High Power Oscillator Configuration Register; Power Mode Configuration Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262
Bits Bit Name Settings
1 HFOSCEN
0 LFOSCEN

HIGH POWER OSCILLATOR CONFIGURATION REGISTER

Address: 0x400C20BC, Reset: 0x00000024, Name: HPOSCCON
Table 19. Bit Descriptions for HPOSCCON
Bits Bit Name Settings
[31:3] Reserved
2 CLK32MHZEN
[1:0] Reserved

POWER MODE CONFIGURATION REGISTER

Address: 0x400C22F0, Reset: 0x00000000, Name: PMBW
This register configures the high and low power system mode for the high speed DAC and ADC circuits.
Table 20. Bit Descriptions for PMBW
Bits Bit Name Settings
[31:4] Reserved
[3:2] SYSBW
00
01
10
11
1 Reserved
0 SYSHP
Description
High Frequency Oscillator Enable. This bit is used to enable or disable the oscillator.
The oscillator must be stable before use. This bit must be set before the
SYSRESETREQ system reset can be initiated.
0 The high frequency oscillator is disabled and placed in a low power state.
1 The high frequency oscillator is enabled.
Low Frequency Oscillator Enable. This bit is used to enable or disable the oscillator.
The oscillator must be stable before use.
0 The low frequency oscillator is disabled and placed in a low power state.
1 The low frequency oscillator is enabled.
Description
Reserved.
16 MHz or 32 MHz Output Selector Signal. Select an output of 32 MHz or 16 MHz.
The ADC can run at 32 MHz, but the system clock cannot run at 32 MHz. Divide
the system clock by 2 first before switching the oscillator to 32 MHz. Refer to
CLKCON0, Bits[5:0].
0 Select 32 MHz output.
1 Select 16 MHz output.
Reserved.
Description
Reserved.
Configure System Bandwidth. Configures the bandwidth of the high speed DAC
reconstruction filter and the ADC antialias filter.
Reserved.
50 kHz, −3 dB bandwidth.
100 kHz, −3 dB bandwidth.
250 kHz, −3 dB bandwidth.
Reserved.
Set High Speed DAC and ADC in High Power Mode.
0 Low power mode. Clear this bit for impedance measurements <80 kHz.
1 High power mode. Set this bit for impedance measurements >80 kHz.
ADuCM355
Rev. B | Page 24 of 312
Hardware Reference Manual
Reset
0x0000000
0x0
0x0
0x0
Reset Access
0x1 R/W
0x1 R/W
Reset Access
0x0 R
0x1 R/W
0x0 R
Access
R
R/W
R
R/W