Transfer Byte Count Registers; Dma Enable Registers - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262
Bits Bit Name Settings
[2:0] IRQMODE
000
001
010
011
100
101
110
111

TRANSFER BYTE COUNT REGISTERS

Address: 0x40004018, Reset: 0x0000, Name: SPI0_CNT
Address: 0x40024018, Reset: 0x0000, Name: SPI1_CNT
This register is only used in master mode.
Table 312. Bit Descriptions for SPI0_CNT, SPI1_CNT
Bits Bit Name Settings
15 FRAMECONT
14 Reserved
[13:0] VALUE

DMA ENABLE REGISTERS

Address: 0x4000401C, Reset: 0x0000, Name: SPI0_DMA
Address: 0x4002401C, Reset: 0x0000, Name: SPI1_DMA
Table 313. Bit Descriptions for SPI0_DMA, SPI1_DMA
Bits Bit Name Settings
[15:3] Reserved
2 RXEN
Description
SPI IRQ Mode Bits. These bits configure when the transmit or receive interrupts occur in a
transfer. For DMA receive transfer, these bits are 0b000.
Transmit interrupt occurs when 1 byte has been transferred. Receive interrupt occurs
when 1 or more bytes have been received into the FIFO.
Transmit interrupt occurs when 2 bytes have been transferred. Receive interrupt occurs
when 2 or more bytes have been received into the FIFO.
Transmit interrupt occurs when 3 bytes have been transferred. Receive interrupt occurs
when 3 or more bytes have been received into the FIFO.
Transmit interrupt occurs when 4 bytes have been transferred. Receive interrupt occurs
when 4 or more bytes have been received into the FIFO.
Transmit interrupt occurs when 5 bytes have been transferred. Receive interrupt occurs
when 5 or more bytes have been received into the FIFO.
Transmit interrupt occurs when 6 bytes have been transferred. Receive interrupt occurs
when 6 or more bytes have been received into the FIFO.
Transmit interrupt occurs when 7 bytes have been transferred. Receive interrupt occurs
when 7 or more bytes have been received into the FIFO.
Transmit interrupt occurs when 8 bytes have been transferred. Receive interrupt occurs
when the FIFO is full.
Description
Continue Frame. Use this bit in conjunction with the SPIx_CTL, Bit 11 and SPIx_CNT,
Bits[13:0] fields. This bit is used to control SPI data framing.
0 When writing to this bit, if this bit is cleared, the SPI master transfers only one frame
of SPIx_CNT, Bits[13:0]. When reading this bit, if the value bits > 0, stop SPI transfers
after the specified number of bytes.
1 When writing to this bit, the SPI master transfers data in frames of SPIx_CNT,
Bits[13:0] bytes per frame. If SPIx_CNT, Bits[13:0] = 0, this field has no effect because
the SPI master continues with transfers as long as the transmit or receive FIFO is
ready. If SPIx_CTL, Bit 11 = 0, this field has no effect because all SPI frames are a
single byte wide, irrespective of other control fields. When reading this bit, continue
SPI transfers as long as the transmit or receive FIFO is ready.
Reserved.
Transfer Byte Count. This field specifies the number of bytes to be transferred. It is
used in both receive and transmit transfer types. This value ensures that a master
mode transfer terminates at the proper time and that 16-bit SPIx_DMA transfers are
byte padded or discarded as required to match odd transfer counts. Reset by
clearing SPIx_CTL, Bit 0 to 0.
Description
Reserved.
Enable Receive DMA Request.
0 Disable receive DMA interrupt.
1 Enable receive DMA interrupt.
ADuCM355
Rev. B | Page 252 of 312
Hardware Reference Manual
Reset
0x0
0x0
Reset Access
0x0 R/W
Reset Access
0x0 R/W
0x0 R
0x0 R/W
Access
R
R/W