Interrupt Enable Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262
Bits Bit Name
2 CMDCOMP
1 WRCLOSE
0 CMDBUSY

INTERRUPT ENABLE REGISTER

Address: 0x40018004, Reset: 0x40, Name: IEN
Used to specify when interrupts are generated.
Table 225. Bit Descriptions for IEN
Bits Bit Name Settings
[31:8] Reserved
[7:6] ECC_ERROR
[5:4] ECC_CORRECT
3 Reserved
2 CMDFAIL
1 WRALCMPLT
0 CMDCMPLT
Settings Description
Command Complete. This bit asserts when a command completes. It
automatically clears when a new command is requested. Following a POR, the
flash controller performs a number of operations, such as verifying the
integrity of code in information space. At the conclusion of this process, the
controller sets this bit to indicate that the process has completed.
Write Registers are Closed. The write data registers (KH_DATA0 and KH_DATA1),
address register (KH_ADDR), and command register (CMD) are closed for
access. This bit is asserted part of the time while a write is in progress. If this bit
is high, the related registers are in use by the flash controller and cannot be
written. This bit clears when the WRALCOMP flag goes high, indicating that
the ongoing write command has consumed the associated data and these
registers can now be overwritten with new data.
Command Busy. This bit is asserted when the flash block is actively executing
any command entered via the command register. There is a slight delay between
requesting a command and this bit asserting. Watch the CMDCOMP bit rather
than this bit when polling for command completion.
Description
Reserved.
Control Whether to Generate Bus Errors, Interrupts, or Neither in Response to 2-Bit
ECC Error Events.
0 Do not generate a response to ECC events.
1 Generate bus errors in response to ECC events.
10 Generate IRQs in response to ECC events.
Control Whether to Generate Bus Errors, Interrupts, or Neither in Response to 1-Bit
ECC Correction Events.
0 Do not generate a response to ECC events.
1 Generate bus errors in response to ECC events.
10 Generate IRQs in response to ECC events.
Reserved.
Command Fail Interrupt Enable. If this bit is set, an interrupt is generated when a
command or flash write completes with an error status.
Write Almost Complete Interrupt Enable.
Command Complete Interrupt Enable. When set, an interrupt is generated when a
command or flash write completes.
ADuCM355
Rev. B | Page 198 of 312
Hardware Reference Manual
Reset Access
0x0 R/W1C
0x0 R
0x0 R
Reset Access
0x0 R
0x1 R/W
0x0 R/W
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W