Control For Retention Sram During Hibernate Mode Register; Hpbuck Control Register; Control For Sram Parity And Instruction Sram Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

CONTROL FOR RETENTION SRAM DURING HIBERNATE MODE REGISTER

Address: 0x4004C014, Reset: 0x00000000, Name: SRAMRET
Table 27. Bit Descriptions for SRAMRET
Bits Bit Name Settings
[31:2] Reserved
1 BNK2EN
0 BNK1EN
HIGH POWER BUCK CONTROL REGISTER
Address: 0x4004C044, Reset: 0x00000000, Name: CTL1
Table 28. Bit Descriptions for CTL1
Bits Bit Name
[31:1] Reserved
0 HPBUCKEN

CONTROL FOR SRAM PARITY AND INSTRUCTION SRAM REGISTER

Address: 0x4004C260, Reset: 0x80000000, Name: SRAM_CTL
Table 29. Bit Descriptions for SRAM_CTL
Bits Bit Name Settings
31 INSTREN
[30:22] Reserved
21 PENBNK5
20 PENBNK4
19 PENBNK3
18 PENBNK2
Description
Reserved.
Enable Retention Bank 2 (16 kB). Bank address is 0x10000000 to 0x10003FFF if SRAM_CTL,
Bit 31 = 1. Bank address is 0x20004000 to 0x20007FFF if SRAM_CTL, Bit 31 = 0.
0 Disable retention of SRAM Bank 2.
Enable retention of SRAM Bank 2 during hibernate mode. This option consumes more
1
power.
Enable Retention Bank 1 (8 kB). Bank address is 0x20002000 to 0x20003FFF.
0 Disable retention of SRAM Bank 1.
1 Enable retention of SRAM Bank 1 during hibernate mode. This option consumes more
power.
Settings Description
Reserved.
Enable High Power Buck.
0 Buck regulator is disabled.
1 Buck regulator is enabled.
Description
Enables Instruction SRAM.
1 CPU instructions use SRAM address range of 0x10000000 to 0x10003FFF.
0 SRAM used for data.
Reserved.
Enable Parity Check for SRAM Bank 5.
0 Disable parity check of this bank of SRAM.
1 Enable parity check of this bank of SRAM.
Enable Parity Check for SRAM Bank 4.
0 Disable parity check of this bank of SRAM.
1 Enable parity check of this bank of SRAM.
Enable Parity Check for SRAM Bank 3.
0 Disable parity check of this bank of SRAM.
1 Enable parity check of this bank of SRAM.
Enable Parity Check for SRAM Bank 2. SRAM Address 0x10000000 to Address 0x10003FFF if
SRAM_CTL, Bit 31 = 1. Address range is 0x20004000 to 0x20007FFF if SRAM_CTL, Bit 31 = 0.
Parity is checked when data is read and when a byte or half word data is written to this
SRAM area. If a parity error is detected, a bus error is generated and the execution
vectors to the bus fault interrupt.
0 Disable parity check of this bank of SRAM.
1 Enable parity check of this bank of SRAM.
ADuCM355
Rev. B | Page 32 of 312
Hardware Reference Manual
Reset
0x00000000
0x0
Reset Access
0x0 R
0x0 R/W
0x0 R/W
Access
R/W
R/W
Reset Access
0x1 R/W
0x000 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W