Channel Software Request Register; Channel Request Mask Set Register; Channel Request Mask Clear Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

CHANNEL SOFTWARE REQUEST REGISTER

Address: 0x40010014, Reset: 0x00000000, Name: SWREQ
The SWREQ register enables the generation of a software DMA request. Each bit of the register represents the corresponding channel
number in the DMA controller. M is the number of DMA channels.
Table 201. Bit Descriptions for SWREQ
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN

CHANNEL REQUEST MASK SET REGISTER

Address: 0x40010020, Reset: 0x00000000, Name: RMSK_SET
Table 202. Bit Descriptions for RMSK_SET
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN

CHANNEL REQUEST MASK CLEAR REGISTER

Address: 0x40010024, Reset: 0x00000000, Name: RMSK_CLR
Table 203. Bit Descriptions for RMSK_CLR
Bits Bit Name Settings
[31:24] Reserved
[23:0] CHAN
Description
Reserved.
Generate Software Request. Set the appropriate bit to generate a software DMA
request on the corresponding DMA channel. Bit 0 corresponds to DMA Channel 0.
Bit M − 1 corresponds to the DMA Channel M – 1. These bits are automatically cleared
by the hardware after the corresponding software request completes.
0 DMA request is not created for Channel C.
1 DMA request is created for Channel C.
Description
Reserved.
Mask Requests from DMA Channels. This register disables DMA requests from
peripherals. Each bit of the register represents the corresponding channel
number in the DMA controller. Set the appropriate bit to mask the request from
the corresponding DMA channel. Bit 0 corresponds to DMA Channel 0. Bit M – 1
corresponds to DMA Channel M – 1.
0 When read as 0, requests are enabled for Channel C. When written as 0, no effect.
1 When read as 1, requests are disabled for Channel C. When written as 1,
peripherals associated with Channel C are disabled from generating DMA
requests.
Description
Reserved.
Clear Request Mask Set Bits. This register enables DMA requests from peripherals
by clearing the mask set in the RMSK_SET register. Each bit of the register
represents the corresponding channel number in the DMA controller. Set the
appropriate bit to clear the corresponding bit in RMSK_SET, Bits[23:0]. Bit 0
corresponds to DMA Channel 0. Bit M – 1 corresponds to DMA Channel M – 1.
0 No effect. Use the RMSK_SET register to disable DMA requests.
1 Peripherals associated with Channel C are enabled to generate DMA requests.
ADuCM355
Rev. B | Page 178 of 312
Hardware Reference Manual
Reset
0x00
0x000000
Reset
0x00
0x000000
Reset
0x00
0x000000
Access
R
W
Access
R
R/W
Access
R
W