Analog Devices ADuCM355 Hardware Reference Manual page 243

ADuCM355 Hardware Reference Manual
In continuous mode, if SPIx_CNT, Bits[13:0] > 0 and SPIx_CNT, Bit 15 = 1, a read of the receive FIFO at the end of an SPI frame always
initiates a new SPI frame. To stop SPI transfers at any given frame, clear the SPIx_CNT, Bit 15 before reading the final set of receive bytes.
The SPI transfer protocol diagrams illustrate the data transfer protocol for the SPI and the effects of the CPHA and CPOL bits in the
control register (SPIx_CTL) on that protocol. See Figure 61 and Figure 62.
CLOCK
CYCLE
NUMBER
SPI CLOCK
(CPOL = 0)
SPI CLOCK
(CPOL = 1)
MOSI
(FROM XX
MASTER)
MISO
(FROM XX
SLAVE)
CS
CLOCK
CYCLE
NUMBER
SPI CLOCK
(CPOL = 0)
SPI CLOCK
(CPOL = 1)
MOSI
(FROM XX
MASTER)
MISO
XX
(FROM
SLAVE)
CS
Transfers in Slave Mode
In slave mode, a transfer is initiated by the assertion of the chip select of the device. Though the master can support up to four chip select
output lines, only one chip select input is used in slave mode. The device as a slave transmits and receives 8-bit data until the transfer is
concluded by the deassertion of chip select. The SPI transfer protocol diagrams in Figure 61 and Figure 62 illustrate the data transfer protocol for
the SPI, and the effects of SPIx_CTL, Bit 2 and SPIx_CTL, Bit 3 on that protocol. The chip select must not be tied to the ground.
SPI Data Underrun and Overflow
If the transmit zeros enable bit (SPIx_CTL, Bit 7) is cleared, the last byte from the previous transmission is shifted out when a transfer is
initiated with no valid data in the FIFO. If SPIx_CTL, Bit 7 is set to 1, 0s are transmitted when a transfer is initiated with no valid data in
the FIFO. If the receive overflow overwrite enable bit (SPIx_CTL, Bit 8) is set, and there is no space left in the FIFO, the valid data in the
receive FIFO is overwritten by the new serial byte received. If SPIx_CTL, Bit 8 is cleared, and there is no space left in the FIFO, the new
serial byte received is discarded. When SPIx_CTL, Bit 8 is set, the contents of the SPI receive FIFO are undefined, and its contents must
be discarded by user code.
1 2 3
MSB 6 5
MSB 6 5
Figure 61. SPI Transfer Protocol, CPHA = 0
1 2 3
MSB 6 5
MSB 6 5
Figure 62. SPI Transfer Protocol, CPHA = 1
Rev. B | Page 243 of 312
4 5 6
4 3 2
4 3 2
4 5 6
4 3 2
4 3 2
7 8
1 LSB XX
1 LSB XX
7 8
1 LSB XX
1 LSB XX
UG-1262