Analog Devices ADuCM355 Hardware Reference Manual page 170

UG-1262
Memory Scatter Gather (CHNL_CFG, Bits[2:0] = 100 or 101)
In memory scatter gather mode, the controller must be configured to use both the primary and alternate data structures. The controller
uses the primary data structure to program the control configuration for the alternate data structure. The alternate data structure is used
for actual data transfers, which are similar to an autorequest DMA transfer. The controller arbitrates after every primary transfer. The
controller requires only one request to complete the entire transfer. This mode is used when performing multiple memory to memory
copy tasks. The MCU can configure all of the tasks simultaneously and does not need to intervene in between each task. The controller
generates the corresponding DMA channel interrupt in the NVIC when the entire scatter gather transaction completes using a basic cycle.
In memory scatter gather mode, the controller receives an initial request and then performs four DMA transfers using the primary data
structure to program the control structure of the alternate data structure. After these transfers complete, the controller starts a DMA
cycle using the alternate data structure. After the cycle completes, the controller performs another four DMA transfers using the primary
data structure. The controller continues to alternate between using the primary and alternate data structures until the processor
configures the alternate data structure for a basic cycle or the DMA reads an invalid data structure.
Table 194 details the fields of the CHNL_CFG memory location for the primary data structure, which must be programmed with
constant values for the memory scatter gather mode. This mode is also shown in Figure 46.
Table 194. CHNL_CFG for Primary Data Structure in Memory Scatter Gather Mode, CHNL_CFG, Bits[2:0] = 100
Bit(s) Name
[31:30] DST_INC
[29:28] Reserved
[27:26] SRC_INC
[25:24] SRC_SIZE
[23:18] Reserved
[17:14] R_POWER
[13:4] N_MINUS_1
3 Reserved
[2:0] CYCLE_CTRL
Description
Set to 10, configures the controller to use word increments for the address.
Undefined. Write as 0.
Set to 10, configures the controller to use word increments for the address.
Set to 10, configures the controller to use word transfers.
Undefined. Write as 0.
Set to 0010, indicates that the DMA controller is ready to perform four transfers.
Configures the controller to perform N DMA transfers, where N is a multiple of four.
Undefined. Write as 0.
Set to 100, configures the controller to perform a memory scatter gather DMA cycle.
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ADuCM355 Hardware Reference Manual