UG-1262
AFE GPIO PORT OUTPUT ENABLE REGISTER
Address: 0x400C0084, Reset: 0x0, Name: OEN
Table 274. Bit Descriptions for OEN
Bits
Bit Name
Settings
[15:3]
Reserved
2
OEN1
[1:0]
OEN0
AFE GPIO PORT OUTPUT PULL-UP AND PULL-DOWN ENABLE REGISTER
Address: 0x400C0088, Reset: 0x2, Name: PE
Table 275. Bit Descriptions for PE
Bits
Bit Name
Settings
[15:3]
Reserved
[2:0]
PE
AFE GPIO PORT INPUT PATH ENABLE REGISTER
Address: 0x400C008C, Reset: 0x0, Name: IEN
Table 276. Bit Descriptions for IEN
Bits
Bit Name
Settings
[15:2]
Reserved
[1:0]
IEN
AFE GPIO PORT REGISTERED DATA INPUT
Address: 0x400C0090, Reset: 0x0, Name: IN
Table 277. Bit Descriptions for IN
Bits
Bit Name
Settings
[15:2]
Reserved
[1:0]
IN
AFE GPIO PORT DATA OUTPUT REGISTER
Address: 0x400C0094, Reset: 0x0, Name: OUT
Table 278. Bit Descriptions for OUT
Bits
Bit Name
Settings
[15:2]
Reserved
[1:0]
OUT
Description
Reserved.
Output Enable for AFE Die Clock to Digital Die. The AFE die Pad P2.2 is internally
connected to the digital die internal Pad P1.10.
0
Disconnects AFE die clock path from digital die P1.10 internal pad.
1
Enables path for AFE die clock to digital die.
Pin Output Drive Enable. Each bit is set to enable the output for that particular pin.
These bits are cleared to disable the output for each pin.
Description
Reserved.
Pin Pull Enable. Each bit is set to enable the pull-up resistor and pull-down resistor
for that particular pin. The bit is cleared to disable the pull-up resistor and pull-down
resistor for each pin.
Description
Reserved.
Input Path Enable. Each bit is set to enable the input path and is cleared to disable
the input path for the GPIO pin.
Description
Reserved.
Registered Data Input. Each bit reflects the state of the GPIO pin if the corresponding
input buffer is enabled. If the pin input buffer is disabled, the value shown is zero.
Description
Reserved.
Data Out. Set by user code to drive the corresponding GPIO high. Cleared by user to
drive the corresponding GPIO low.
ADuCM355
Rev. B | Page 224 of 312
Hardware Reference Manual
Reset
Access
0x0000
R/W
0
R/W
0x0
R/W
Reset
Access
0x0000
R/W
0x0
R/W
Reset
Access
0x0000
R/W
0x0
R/W
Reset
Access
0x0000
R/W
0x0
R
Reset
Access
0x0000
R/W
0x0
R/W
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