Serial Wire Debug Interface - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

SERIAL WIRE DEBUG INTERFACE

The SWD interface provides a debug port for pin limited packages. The SWD replaces the 5-pin JTAG port with the SWCLK pin and a
single bidirectional data pin (SWDIO), providing all the normal JTAG debug and test functionality. SWDIO and SWCLK are overlaid on
the TMS and TCK pins, respectively, on the Arm 20-pin JTAG interface (see Figure 68).
Table 411. SWD Connections
Signal Connection
SWDIO Data input/output pin. Use a 100 kΩ pull-up resistor to V
SWO No connect.
SWCLK Clock pin. Use a 100 kΩ pull-up resistor to V
V Positive supply voltage. Power supply for JTAG interface drivers.
CC
GND Digital ground.
RESET No connect.
NYU No connect, not used.
2
I C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.
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V 1
CC
NYU 3
NYU 5
SWDIO 7
SWCLK 9
NYU 11
SWO 13
RESET 15
NYU 17
NYU 19
Figure 68. SWD 20-Pin Connector Pinout
from SWCLK.
CC
UG16675-2/20(B)
Rev. B | Page 312 of 312
ADuCM355 Hardware Reference Manual
2 V (OPTIONAL)
CC
4 GND
6 GND
8 GND
10 GND
12 GND
14 GND
16 GND
18 GND
20 GND
from SWDIO.
CC