Analog Die Circuitry Summary; Adc, High Speed Dac, And Associated Amplifiers Operating Mode Configuration; System Bandwidth Configuration - Analog Devices ADuCM355 Hardware Reference Manual

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ANALOG DIE CIRCUITRY SUMMARY

The ADuCM355 analog die includes the following eight main blocks:

ADC. The ADC is a high speed SAR ADC with a wide range of voltage and current input channels. See the ADC Circuit section.

Low power potentiostat and TIA. This block also includes the low power DACs used to set the dc bias voltage of an external
electrochemical sensor. See the Low Power Potentiostat Amplifiers and Low Power TIA section.

High speed TIA. The high speed TIA is intended for measuring ac current signals with the ADC, especially during impedance
measurements. The high speed TIA supports a wider input signal bandwidth than the low power TIA. The current consumption of
the high speed TIA is higher than that of the low power TIA. See the High Speed TIA Circuits section.

High speed DAC circuits. The high speed DAC is designed to support ac impedance measurements with its specially designed
output excitation amplifier. The ac signal from the output of the high speed DAC can be coupled on the dc sensor bias voltage set by
the low power DAC via the excitation amplifier. See the High Speed DAC Circuits section.

Programmable switches connecting external sensor to the high speed DAC and the high speed TIA. The
flexibility in connecting external pins to the high speed TIA and excitation amplifier terminals. See the Programmable Switches
Connecting the External Sensor to the High Speed DAC and High Speed TIA section.

Analog die digital circuits. This block includes optional programmable timers. See the Analog Die General-Purpose Timers section.

Use case configurations. The Use Case Configurations section describes typical electrochemical sensor use cases and the
configuration of the ADuCM355

Sequencer (see the Sequencer section).

ADC, HIGH SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

The ADC and high speed DAC circuits are flexible in trading current consumption vs. signal bandwidth. If the ADC and high speed
DACs are used to measure and generate signals <80 kHz for low frequency impedance measurements, these blocks can be configured for
low power mode by clearing PMBW, Bit 0 = 0. This configuration minimizes power consumption. If the ADC and or high speed DAC
are used to measure and generate signals >80 kHz for high frequency impedance measurements, set PMBW, Bit 0 = 1.

SYSTEM BANDWIDTH CONFIGURATION

The user must configure the bandwidth setting for the reconstruction filter of the high speed DAC, the antialias filter of the ADC, and
the bandwidth of the high speed TIA, in addition to configuring PMBW Bit 0. PMBW, Bits[3:2] allow the user to set this configuration.
For the HSTIACON register, ensure that HSTIACON, Bits[5:1] = 00000 in low power mode and HSTIACON, Bits[5:1] = 11111 in high power
mode. See Table 20 for more details on the PMBW register.
for each use case.
Rev. B | Page 52 of 312
ADuCM355 Hardware Reference Manual
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