Analog Devices ADuCM355 Hardware Reference Manual page 136

UG-1262
Data FIFO Read Register
Address: 0x400C206C, Reset: 0x00000000, Name: DATAFIFORD
Table 160. Bit Descriptions for DATAFIFORD Register
Bits Bit Name
[31:0] DATAFIFOOUT
Command FIFO Write Register
Address: 0x400C2070, Reset: 0x00000000, Name: CMDFIFOWRITE
Table 161. Bit Descriptions for CMDFIFOWRITE Register
Bits Bit Name Description
[31:0] CMDFIFOIN Command FIFO Write. If the command FIFO is written when full, the write is ignored and no
current commands are affected.
Sequencer Sleep Control Lock Register
Address: 0x400C2118, Reset: 0x00000000, Name: SEQSLPLOCK
The SEQSLPLOCK register protects the SEQTRGSLP register.
Table 162. Bit Descriptions for SEQSLPLOCK Register
Bits Bit Name Settings
[31:20] Reserved
[19:0] SEQ_SLP_PW
0xA47E5
Sequencer Trigger Sleep Register
Address: 0x400C211C, Reset: 0x00000000, Name: SEQTRGSLP
The SEQTRGSLP register is protected by the SEQSLPLOCK register.
Table 163. Bit Descriptions for SEQTRGSLP Register
Bits Bit Name Description
[31:1] Reserved Reserved.
0 TRGSLP Trigger Sleep by Sequencer. Write to the SEQSLPLOCK register first. Put this command at the end of a
sequence. Set this command to 1 if entering sleep at the end of a sequence.
Sequence 0 Information Register
Address: 0x400C21CC, Reset: 0x00000000, Name: SEQ0INFO
Table 164. Bit Descriptions for SEQ0INFO Register
Bits Bit Name
[31:27] Reserved
[26:16] SEQ0INSTNUM
[15:11] Reserved
[10:0] SEQ0STARTADDR
Description
Data FIFO Read. When the data FIFO is empty, a read of this register returns 0x00000000. See
Figure 32 and Figure 33 for word format details.
Description
Reserved.
SEQTRGSLP Register Password. These bits prevent the sequencer from
accidentally triggering a sleep state.
0x400C Write any value other than 0xA47E5 to lock the SEQTRGSLP register.
Write this value to this register to unlock the SEQTRGSLP register.
Description
Reserved.
SEQ0 Instruction Number.
Reserved.
SEQ0 Start Address.
ADuCM355
Rev. B | Page 136 of 312
Hardware Reference Manual
Reset
0x0
0x0
0x0
0x0
Reset Access
0x0 R
Reset Access
0x0 W
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
Access
R
R/W
R
R/W