Interrupt Configuration Registers - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual
Bits Bit Name Settings
3 CPOL
2 CPHA
1 MASEN
0 SPIEN

INTERRUPT CONFIGURATION REGISTERS

Address: 0x40004014, Reset: 0x0000, Name: SPI0_IEN
Address: 0x40024014, Reset: 0x0000, Name: SPI1_IEN
Table 311. Bit Descriptions for SPI0_IEN, SPI1_IEN
Bits Bit Name Settings
15 Reserved
14 TXEMPTY
0
1
13 XFRDONE
0
1
12 TXDONE
0
1
11 RDY
0
1
10 RXOVR
0
1
9 TXUNDR
0
1
8 CS
0
1
[7:3] Reserved
Description
Serial Clock Polarity.
0 Serial clock idles low.
1 Serial clock idles high.
Serial Clock Phase Mode.
0 Serial clock pulses at the end of each serial bit transfer.
1 Serial clock pulses at the beginning of each serial bit transfer.
Master Mode Enable.
0 Enable slave mode.
1 Enable master mode.
SPI Enable.
0 Disable the SPI.
1 Enable the SPI.
Description
Reserved.
Transmit FIFO Empty Interrupt Enable. This bit enables the SPIx_STAT, Bit 2 interrupt
whenever the transmit FIFO is emptied.
TXEMPTY interrupt is disabled.
TXEMPTY interrupt is enabled.
SPI Transfer Completion Interrupt Enable. This bit enables the SPIx_STAT, Bit 1 interrupt.
XFRDONE interrupt is disabled.
XFRDONE interrupt is enabled.
SPI Transmit Done Interrupt Enable. This bit enables the SPIx_STAT, Bit 3 interrupt in read
command mode. This interrupt can be used to signal the change of SPI transfer direction
in read command mode.
TXDONE interrupt is disabled.
TXDONE interrupt is enabled.
Ready Signal Edge Interrupt Enable. This bit enables the SPIx_STAT, Bit 15 interrupt
whenever an active edge occurs on P0.3 signals. If SPIx_FLOW_CTL, Bits[1:0] = 0b10, this
bit is set whenever an active edge is detected on the P0.3 signal. If SPIx_FLOW_CTL,
Bits[1:0] = 0b11, this bit is set if an active edge is detected on the MISO signal. If
SPIx_FLOW_CTL, Bits[1:0] = 0b00 or 0b01, this bit is always 0. The active edge (rising or
falling) is determined by SPIx_FLOW_CTL, Bit 4.
Ready signal edge interrupt is disabled.
Ready signal edge interrupt is enabled.
Receive Overflow Interrupt Enable.
Receive overflow interrupt is disabled.
Receive overflow interrupt is enabled.
Transmit Underflow Interrupt Enable.
Transmit underflow interrupt is disabled.
Transmit underflow interrupt is enabled.
Enable Interrupt on Every Chip Select Edge in Slave Continuous Mode.
No interrupt is generated and the status bits are not asserted.
If the SPI module is configured as a slave in continuous mode, any edge on chip select
generates an interrupt and the corresponding status bits (SPIx_STAT, Bit 14 and
SPIx_STAT, Bit 13) are asserted. This bit has no effect if the SPI is not in continuous mode
or if it is a master.
Reserved.
Rev. B | Page 251 of 312
UG-1262
Reset Access
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R