UG-1262
Bits
Bit Name
Settings
[2:1]
TYPESEL
0
Reserved
WAVEFORM GENERATOR FOR SINUSOID FREQUENCY CONTROL WORD REGISTER
Address: 0x400C2030, Reset: 0x00000000, Name: WGFCW
Table 139. Bit Descriptions for WGFCW
Bits
Bit Name
Settings
[31:24]
Reserved
[23:0]
SINEFCW
WAVEFORM GENERATOR FOR SINUSOID PHASE OFFSET REGISTER
Address: 0x400C2034, Reset: 0x00000000, Name: WGPHASE
Table 140. Bit Descriptions for WGPHASE
Bits
Bit Name
Settings
[31:20]
Reserved
[19:0]
SINEOFFSET
WAVEFORM GENERATOR FOR SINUSOID OFFSET REGISTER
Address: 0x400C2038, Reset: 0x00000000, Name: WGOFFSET
Table 141. Bit Descriptions for WGOFFSET
Bits
Bit Name
Settings
[31:12]
Reserved
[11:0]
SINEOFFSET
WAVEFORM GENERATOR FOR SINUSOID AMPLITUDE REGISTER
Address: 0x400C203C, Reset: 0x00000000, Name: WGAMPLITUDE
Table 142. Bit Descriptions for WGAMPLITUDE
Bits
Bit Name
[31:11]
Reserved
[10:0]
SINEAMPLITUDE
Description
Selects the Type of Waveform.
00
Direct write to DAC. User code writes to the HSDACDAT register directly.
10
Sinusoid. Set AFECON, Bit 4 to 1, set this bit to 10, and the DAC outputs a sine wave.
11, 01
Reserved.
Reserved. Clear to 0 always.
Description
Reserved.
Sinusoid Generator Frequency Control Word. Selects the output frequency of the
sinusoid waveform. By default, the output frequency ACLK frequency × (SINEFCW/2
Description
Reserved.
Sinusoid Phase Offset. SINOFFSET, Bits[19:0] = phase (degrees)/360 × 2
example, to achieve a 45° phase offset, SINOFFSET, Bits[19:0] = 45/360 × 2
MMR must be set before setting WGCON, Bits[2:1] and AFECON, Bit 14.
Description
Reserved.
Sinusoid Offset. Added to the waveform generator output in sinusoid mode. Signed
number represented in twos complement format. This MMR must be set before setting
WGCON, Bits[2:1] and AFECON, Bit 14.
Settings
Description
Reserved.
Sinusoid Amplitude. Unsigned number. Scales the waveform generator in
sinusoid mode. The DAC output voltage is determined by the value in
HSDACCON, Bit 0 and HSDACCON, Bit 12. This MMR must be set before setting
WGCON, Bits[2:1] and AFECON, Bit 14.
ADuCM355
Rev. B | Page 116 of 312
Hardware Reference Manual
30
).
20
. For
20
. This
Reset
Access
0x0
R/W
0x0
W
Reset
Access
0x0
R
0x0
R/W
Reset
Access
0x0
R
0x0
R/W
Reset
Access
0x0
R
0x0
R/W
Reset
Access
0x0
R
0x0
R/W
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