Analog Devices ADuCM355 Hardware Reference Manual page 155

ADuCM355 Hardware Reference Manual
RE0
CE0
SW3
CAP_POT0
10kΩ
RE0
SW11
SE0
SW1
RC0_0
RC0_1
SE0
SE1
CORRESPONDING TO LPTIASWx[0:15]
FOR RAMP TEST USING HPTIA,
LPTIASWx = 0x0094 (SW2, SW4 CLOSED, SW7 AS SHOWN ABOVE – OTHERS OPENED)
CLOSE SW2 TO SHORT OUTPUT OF POTENTIOSTAT AMPLIFIER TO COUNTER ELECTRODE.
OPEN SW3 TO DISCONNECT RC FILTER FROM SENSOR, EXTERNAL CAPACITOR NOT CONNECTED BETWEEN CAP_POT0 AND CE0.
CLOSE SW4 TO CONNECT RE0 FROM POTENTIOSTAT AMPLIFIER INVERTING INPUT.
OPEN SW5 TO DISCONNECT C
SET SW7 BIT TO SHORT LOW POWER TIA INVERTING INPUT (–) TO THE LOW POWER TIA OUTPUT.
Figure 39. Switches for Low Power Potentiostat, Low Power TIA, and Switch Matrix to Perform Cyclic Voltammetry or Pulse Test on SE0 Node Using High Speed TIA
VBIAS0
LPDACSW0[3]
SW12
SW15
+
PA
SW2
–
SW8
SW10
10kΩ
SW4
R
LOAD
LPTIACON0
[12:10]
R
TIA
LPTIACON0
[9:5]
TSWFULLCON[4]
T5
HSTIA
TSWFULLCON[6]
T7
, WHICH IS THE EXTERNAL CAPACITOR CONNECTED BETWEEN RC0_0 AND RC0_1.
TIA
VZERO0
LPDACSW0[1]
SW13
OPEN: LPDACCON0[5] = 1 LPDACCON0[3]
AND LPDACSW0[4] = 0
12-BIT
VZERO0
6-BIT
LPDACCON0[4]
LPDACSW0[2]
SW6
+
LPTIA
–
SW7
FORCE/SENSE
SW0
LPDACSW1[0]
ADCVBIAS_CAP (1.11V)
LPDACSW0[0]
Rev. B | Page 155 of 312
VREF_2.5V AIN4_LPF0
ULPBUF
LPDAC0
ULPREF
SW14
TO CHANNEL 1
SW5 SW9
R
LPF
LPTIACON0
[15:13]
VZERO1
VZERO0
UG-1262
ADC
MUX