Analog Devices ADuCM355 Hardware Reference Manual page 143

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ADuCM355
Hardware Reference Manual
Bits
Bit Name
Settings
25
FLAG25
24
FLAG24
23
FLAG23
[22:18]
Reserved
17
FLAG17
16
FLAG16
15
FLAG15
14
Reserved
13
FLAG13
12
FLAG12
11
FLAG11
10
FLAG10
9
FLAG9
8
Reserved
7
FLAG7
6
FLAG6
5
FLAG5
Description
Data FIFO Threshold IRQ Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Data FIFO Empty IRQ Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Data FIFO Full IRQ Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Reserved.
Sequencer Timeout Error IRQ Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Sequencer Timeout Finished IRQ Status.
0
Interrupt not asserted.
1
Interrupt asserted.
End of Sequence IRQ Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Reserved.
Bootload Done IRQ Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Custom Interrupt 3 Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Custom Interrupt 2 Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Custom Interrupt 1 Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Custom Interrupt 0 Status.
0
Interrupt not asserted.
1
Interrupt asserted.
Reserved.
Mean IRQ Status.
0
Interrupt not asserted.
1
Interrupt asserted.
ADC Delta Fail IRQ Status. When this bit is set, it indicates that the difference between two
consecutive ADC results is greater than the value specified by the ADCDELTA register. If
this bit is clear, it indicates that no difference between two consecutive ADC values
greater than the limit is detected since the last time this bit was cleared.
0
Interrupt not asserted.
1
Interrupt asserted.
ADC Maximum Fail IRQ Status. When this bit is set, it indicates that an ADC result is
above the maximum value specified by the ADCMAX register. If this bit is clear, it
indicates that no ADC value above the maximum is detected.
0
Interrupt not asserted.
1
Interrupt asserted.
Rev. B | Page 143 of 312
UG-1262
Reset
Access
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R

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