Sequencer And Fifo Registers - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

SEQUENCER AND FIFO REGISTERS

Table 154. Sequence and FIFO Registers Summary
Address Name
0x400C2004 SEQCON
0x400C2008 FIFOCON
0x400C2060 SEQCRC
0x400C2064 SEQCNT
0x400C2068 SEQTIMEOUT
0x400C206C DATAFIFORD
0x400C2070 CMDFIFOWRITE
0x400C2118 SEQSLPLOCK
0x400C211C SEQTRGSLP
0x400C21CC SEQ0INFO
0x400C21D0 SEQ2INFO
0x400C21D4 CMDFIFOWADDR
0x400C21D8 CMDDATACON
0x400C21E0 DATAFIFOTHRES
0x400C21E4 SEQ3INFO
0x400C21E8 SEQ1INFO
0x400C2200 FIFOCNTSTA
0x400C0430 TRIGSEQ
Sequencer Configuration Register
Address: 0x400C2004, Reset: 0x00000002, Name: SEQCON
Table 155. Bit Descriptions for SEQCON Register
Bits Bit Name
[31:16] Reserved
[15:8] SEQWRTMR
[7:5] Reserved
4 SEQHALT
[3:2] Reserved
1 SEQHALTFIFOEMPTY
0 SEQEN
Description
Sequencer configuration register
FIFO configuration register
Sequencer CRC value register
Sequencer command count register
Sequencer timeout counter register
Data FIFO read register
Command FIFO write register
Sequencer sleep control lock register
Sequencer trigger sleep register
Sequence 0 information register
Sequence 2 information register
Command FIFO write address register
Command data control register
Data FIFO threshold register
Sequence 3 information register
Sequence 1 information register
Command and data FIFO internal data count register
Trigger sequence register
Settings Description
Reserved.
Sequencer Write Commands Timer. These bits act as a clock divider
affecting only the write commands, not the wait commands. This divider
is useful to reduce the code size when generating arbitrary waveforms.
The clock source for the timer is ACLK.
Reserved.
Halt Sequence Debugging Feature. This bit provides a way to halt the AFE
interface.
0 Normal execution.
1 Execution halted.
Reserved.
Halt Sequencer. This bit controls whether the sequencer stops when
attempting to read when the command FIFO is empty (in an underflow
condition).
1 Sequencer stops if command FIFO is empty and sequencer attempts to
read (in an underflow condition).
0 Sequencer continues to attempt to read, even if the FIFO is empty.
Enable Sequencer. When this bit is set to 1, the sequencer reads from the
command FIFO and executes the commands.
0 Sequencer disabled (default).
1 Sequencer enabled.
Rev. B | Page 134 of 312
ADuCM355 Hardware Reference Manual
Reset Access
0x00000002 R/W
0x00001010 R/W
0x00000001 R
0x00000000 R/W
0x00000000 R
0x00000000 R
0x00000000 W
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
0x00000410 R/W
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
0x00000000 R
0x0000 R/WS
Reset Access
0x0 R
0x0 R/W
0x0 R
0x0 R/W
0x0 R
0x1 R/W
0x0 R/W