Second Slave Address Device Id Register; Third Slave Address Device Id Register; Fourth Slave Address Device Id Register; Master And Slave Fifo Status Register - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

SECOND SLAVE ADDRESS DEVICE ID REGISTER

Address: 0x40003040, Reset: 0x0000, Name: ID1
Table 298. Bit Descriptions for ID1
Bits Bit Name Settings
[15:8] Reserved
[7:0] ID1

THIRD SLAVE ADDRESS DEVICE ID REGISTER

Address: 0x40003044, Reset: 0x0000, Name: ID2
Table 299. Bit Descriptions for ID2
Bits Bit Name Settings
[15:8] Reserved
[7:0] ID2

FOURTH SLAVE ADDRESS DEVICE ID REGISTER

Address: 0x40003048, Reset: 0x0000, Name: ID3
Table 300. Bit Descriptions for ID3
Bits Bit Name Settings
[15:8] Reserved
[7:0] ID3

MASTER AND SLAVE FIFO STATUS REGISTER

Address: 0x4000304C, Reset: 0x0000, Name: FSTAT
Table 301. Bit Descriptions for FSTAT
Bits Bit Name Settings
[15:10] Reserved
9 MFLUSH
8 SFLUSH
[7:6] MRXF
[5:4] MTXF
Description
Reserved.
Slave Device ID 1. ID1, Bits[7:1] are programmed with the device ID. ID1, Bit 0 is don't care.
See SCTL, Bit 1 to see how this register is programmed with a 10-bit address. Take care to
2
avoid I C reserved slave addresses with values less than 0x10 and greater than 0xF6.
Description
Reserved.
Slave Device ID 2. ID2, Bits[7:1] are programmed with the device ID. ID2, Bit 0 is don't care.
See SCTL, Bit 1 to see how this register is programmed with a 10-bit address. Take care to
2
avoid I C reserved slave addresses with values less than 0x10 and greater than 0xF6.
Description
Reserved.
Slave Device ID 3. ID3, Bits[7:1] are programmed with the device ID. ID3, Bit 0 is don't care.
See SCTL, Bit 1 to see how this register is programmed with a 10-bit address. Take care to
2
avoid I C reserved slave addresses with values less than 0x10 and greater than 0xF6.
Description
Reserved.
Flush the Master Transmit FIFO.
0 No effect.
1 Flush the master transmit FIFO. The master transmit FIFO must be flushed if
arbitration is lost or a slave responds with a no acknowledge.
Flush the Slave Transmit FIFO.
0 No effect.
1 Flush the slave transmit FIFO.
Master Receive FIFO Status. The status is a count of the number of bytes in a FIFO.
00 FIFO empty.
01 1 byte in the FIFO.
10 2 bytes in the FIFO.
11 Reserved.
Master Transmit FIFO Status. The status is a count of the number of bytes in a FIFO.
00 FIFO empty.
01 1 byte in the FIFO.
10 2 bytes in the FIFO.
11 Reserved.
ADuCM355
Rev. B | Page 238 of 312
Hardware Reference Manual
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R
0x0 R/W
Reset Access
0x0 R/W
0x0 W
0x0 W
0x0 R
0x0 R