Receive Registers; Transmit Registers; Baud Rate Selection Registers - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual
Bits Bit Name Settings
3 TXDONE
2 TXEMPTY
1 XFRDONE
0 IRQ

RECEIVE REGISTERS

Address: 0x40004004, Reset: 0x0000, Name: SPI0_RX
Address: 0x40024004, Reset: 0x0000, Name: SPI1_RX
Table 307. Bit Descriptions for SPI0_RX, SPI1_RX
Bits Bit Name Settings
[15:8] BYTE2
[7:0] BYTE1

TRANSMIT REGISTERS

Address: 0x40004008, Reset: 0x0000, Name: SPI0_TX
Address: 0x40024008, Reset: 0x0000, Name: SPI1_TX
Table 308. Bit Descriptions for SPI0_TX, SPI1_TX
Bits Bit Name Settings
[15:8] BYTE2
[7:0] BYTE1

BAUD RATE SELECTION REGISTERS

Address: 0x4000400C, Reset: 0x0000, Name: SPI0_DIV
Address: 0x4002400C, Reset: 0x0000, Name: SPI1_DIV
Table 309. Bit Descriptions for SPI0_DIV, SPI1_DIV
Bits Bit Name Settings
[15:6] Reserved
[5:0] VALUE
Description
SPI Transmit Done in Read Command Mode.
0 Cleared to 0 when 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
Set when the entire transmit is completed in a read command. This bit generates an
1
interrupt if SPIx_IEN, Bit 12 is set, and is only valid if SPIx_RD_CTL, Bit 0 is set.
SPI Transmit FIFO Empty Interrupt.
0 Cleared to 0 when 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
1 Set when the transmit FIFO is empty. This bit generates an interrupt if SPIx_IEN, Bit
14 is set to 1 except when SPIx_CTL, Bit 13 is set.
SPI Transfer Completion. This bit indicates the status of SPI transfer completion in
master mode.
0 Cleared to 0 when 1 is written to this bit.
1 Set when the transfer of SPIx_CNT, Bits[13:0] number of bytes has finished. In slave
mode or if SPIx_CNT, Bits[13:0] = 0, this bit is invalid. If SPIx_IENx, Bit 13 is set, this bit
generates an interrupt. It uses the state of the master state machine to determine the
completion of a SPI transfer. Therefore, a chip select override does not affect this bit.
SPI Interrupt Status.
0 Cleared to 0 when all SPI interrupt sources are cleared.
1 Set when an SPI based interrupt occurs.
Description
8-Bit Receive Buffer. These 8 bits are used only in DMA mode, where all FIFO accesses
occur as half word accesses. They return 0 if DMA is disabled.
8-Bit Receive Buffer.
Description
8-Bit Transmit Buffer. These 8 bits are used only in DMA mode, where all FIFO accesses
occur as half word accesses. They return 0 if DMA is disabled.
8-Bit Transmit Buffer.
Description
Reserved.
SPI Clock Divider. The clock divider value is the factor used to divide UCLK to generate
the serial clock.
Rev. B | Page 249 of 312
UG-1262
Reset Access
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R
Reset Access
0x0 R
0x0 R
Reset Access
0x0 W
0x0 W
Reset Access
0x0 R
0x0 R/W