External Interrupt Configuration - Analog Devices ADuCM355 Hardware Reference Manual

ADuCM355 Hardware Reference Manual

EXTERNAL INTERRUPT CONFIGURATION

Two external interrupts are implemented, separate from those described in the Digital Inputs and Outputs section. One of these external
interrupts is the P1.0/SYS_WAKE pin. The other is the interrupt source from the analog die that connects to External Interrupt 3 line of
the digital die, which can be connected to the UART input pin (P0.11/UART_SIN). These two external interrupts can be separately
configured to detect any combination of the following type of events:

Edge: rising edge, falling edge, or both rising and falling edges. An interrupt signal (pulse) is sent to the NVIC upon detecting a
transition from low to high, high to low, or on either high to low or low to high.

Level: high or low. An interrupt signal is generated and remains asserted in the NVIC until the conditions generating the interrupt
deassert. The level must be maintained for a minimum of one core clock cycle to be detected.
The external interrupt detection unit block is in the always on section and allows the external interrupt to wake up the device when in
hibernate mode.
Ensure that the associated GPxIE register bits are enabled for the required external interrupt input. The GPxIE registers enable the input
path circuit for the external interrupt.
For example, for External Interrupt 1 (SYS_WAKE), the following code disables the P1.0/SYS_WAKE output pin and enables the input
path. The appended code also enables the External Interrupt 1 NVIC interrupt source.
pADI_GPIO1->OEN &= 0xFFFE;
pADI_GPIO1->IEN |= 0x0001;
pADI_XINT0->CFG0 |=0x80;
NVIC_EnableIRQ(XINT_EVT1_IRQn);
//Disable P1.0 output.
//Enable input path for P1.0 input.
//External IRQ1 enabled.
//Enable External Interrupt 1 source.
Rev. B | Page 47 of 312
UG-1262