Analog Devices ADuCM355 Hardware Reference Manual page 135

ADuCM355 Hardware Reference Manual
FIFO Configuration Register
Address: 0x400C2008, Reset: 0x00001010, Name: FIFOCON
Table 156. Bit Descriptions for FIFOCON Register
Bits Bit Name
[31:16] RESERVED
[15:13] DATAFIFOSRCSEL
12 Reserved
11 DATAFIFOEN
[10:0] Reserved
Sequencer CRC Value Register
Address: 0x400C2060, Reset: 0x00000001, Name: SEQCRC
The SEQCRC register forms the checksum value calculated from all the commands executed by the sequencer.
Table 157. Bit Descriptions for SEQCRC Register
Bits Bit Name
[31:8] Reserved
[7:0] CRC
Sequencer Command Count Register
Address: 0x400C2064, Reset: 0x00000000, Name: SEQCNT
The SEQCNT register forms the command count, which is incremented by 1 each time the sequencer executes a command. This register
is not key protected.
Table 158. Bit Descriptions for SEQCNT Register
Bits Bit Name Description
[31:16] Reserved Reserved.
[15:0] Count Sequencer Command Count. This count is incremented by 1 each time the sequencer executes a
command. To reset to 0 or clear the SEQCRC register, write 1 to this register.
Sequencer Timeout Counter Register
Address: 0x400C2068, Reset: 0x00000000, Name: SEQTIMEOUT
Table 159. Bit Descriptions for SEQTIMEOUT Register
Bits Bit Name
[31:30] Reserved
[29:0] Timeout
Settings Description
Reserved.
Data FIFO Source Select.
000, 001, ADC data. The ADC data is the output of the sinc3 filter.
110, or 111
010 DFT data. The real part is 18 bits, and the imaginary part is 18 bits. The lowest
two bits are fractional because the ADC is 16 bits.
011 Sinc2 filter output, data is 16 bits.
100 Statistic variance output.
101 Mean result, mean is 16 bits of data.
Reserved.
Data FIFO Enable.
0 FIFO is reset, no data transfers can take place. This setting sets the read
and write pointers to the default values (FIFO empty). The status
indicates that the FIFO is empty.
1 Normal operation, the FIFO is not reset.
Reserved.
Description
Reserved.
Sequencer Command CRC Value. The algorithm used is CRC-8.
Description
Reserved.
Sequencer Timeout Counter Current Value.
Rev. B | Page 135 of 312
UG-1262
Reset Access
0x0 R
0x0 R/W
0x1 R/W
0x0 R/W
0x0 R/W
Reset Access
0x0 R
0x1 R
Reset Access
0x0 R
0x0 R/W1
Reset Access
0x0 R
0x0 R