Analog Devices ADuCM355 Hardware Reference Manual page 207

ADuCM355 Hardware Reference Manual
Initialization of more SRAM banks, where parity is enabled, can be achieved at any time by writing to the SRAM_CTL register. Set the
appropriate SRAM_CTL, Bits[5:0] for SRAM banks that need parity to be enabled to 1. Also, set SRAM_CTL, Bit 13 to 1. SRAM_CTL,
Bit 13 is autocleared to 0 after being written and triggers the initialization sequence.
After exiting hibernate mode, the contents of nonretained SRAM banks are lost. If these banks have parity enabled, initialization is
required. There are two options to initialize the required SRAM banks after exiting hibernate mode as follows:

Initialize by writing to SRAM_CTL, Bit 13 after exiting hibernate mode. The SRAM banks that are set to 1 by SRAM_CTL, Bits[5:0]
are initialized.

Automatic initialization after hibernate mode. There is no write required to SRAM_CTL after hibernate mode. To select automatic
mode, set SRAM_CTL, Bit 14 prior to hibernation or initialization. The SRAMs selected for initialization in this register
automatically initialize after exiting hibernate mode.
Initialization resets the contents of the selected memory banks. It is important that the user carefully select which memory banks are
initialized so no user information is lost. The initialization sequence can be aborted at any time by writing to SRAM_CTL, Bit 15. This bit
is self cleared after it has been written.
Rev. B | Page 207 of 312
UG-1262