Register Details: Spi0/Spi1; Status Registers - Analog Devices ADuCM355 Hardware Reference Manual

UG-1262

REGISTER DETAILS: SPI0/SPI1

STATUS REGISTERS

Address: 0x40004000, Reset: 0x0800, Name: SPI0_STAT
Address: 0x40024000, Reset: 0x0800, Name: SPI1_STAT
Table 306. Bit Descriptions for SPI0_STAT, SPI1_STAT
Bits Bit Name Settings
15 RDY
14 CSFALL
13 CSRISE
12 CSERR
11 CS
[10:8] Reserved
7 RXOVR
6 RXIRQ
5 TXIRQ
4 TXUNDR
Description
Detected an Edge on Ready Indicator for Flow Control. This bit indicates that there
was an active edge on the P0.3 line depending on the flow control mode. If SPIx_FLOW_
CTL, Bits[1:0] = 0b10, this bit is set whenever an active edge is detected on the P0.3
signal. If SPIx_FLOW_CTL, Bits[1:0] = 0b11, this bit is set if an active edge is detected
on the MISO signal.
0 If SPIx_FLOW_CTL, Bits[1:0] = 0b00 or 0b01. The active edge (rising or falling) is
determined by SPI_FLOW_CTL, Bit 4.
When SPIx_IEN, Bit 11 is set to 1, this bit causes an interrupt, which is only cleared by
1
writing 1 to this bit.
Detected a Falling Edge on Chip Select in Slave Continuous Mode. This bit causes an
interrupt when SPIx_IEN, Bit 8 is set to 1, which can be used to identify the start of an
SPI data frame.
0 Cleared to 0 when a 1 is written to this bit.
Set when there is a falling edge on chip select line. Used to identify the start of an SPI
1
data frame.
Detected a Rising Edge on Chip Select in Slave Continuous Mode. This bit causes an
interrupt when SPIx_IEN, Bit 8 is set to 1.
0 Cleared to 0 when a 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
1 Set when there is a rising edge on the chip select line. This bit can be used to identify
the end of an SPI data frame.
Detected a Chip Select Error Condition.
0 Cleared to 0 when a 1 is written to this bit.
1 Set when the chip select line is deasserted abruptly, even before the full byte of data
is transmitted completely. This bit causes an interrupt.
Chip Select Status. This bit reflects the actual chip select status as seen by the SPI
module. This bit uses SCLK to PCLK synchronization. As such, there is a slight delay
when chip select changes state.
0 Chip select line is low.
1 Chip select line is high.
Reserved.
SPI Receive FIFO overflow.
0 Cleared to 0 when a 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
1 Set when the receive FIFO is already full when new data is loaded to the FIFO. This bit
generates an interrupt if SPIx_IEN, Bit 10 = 1, except when SPIx_CTL, Bit 12 is set.
SPI Receive IRQ. Not available in DMA mode.
1 Cleared to 0 when a 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
0 Set when a receive interrupt occurs. This bit is set when TIM in SPIx_CTL, Bit 6 is
cleared and the required number of bytes is received.
SPI Transmit IRQ. Status bit. This bit is not available in DMA mode.
0 Cleared to 0 when a 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
1 Set when a transmit interrupt occurs. This bit is set when SPIx_CTL, Bit 6 is set and the
required number of bytes is transmitted.
SPI Transmit FIFO Underflow.
0 Cleared to 0 when a 1 is written to this bit or when SPIx_CTL, Bit 0 is cleared to 0.
1 Set when a transmit is initiated without any valid data in the transmit FIFO. This bit
generates an interrupt when SPIx_IEN, Bit 9 = 1 except when SPIx_CTL, Bit 13 is set.
ADuCM355
Rev. B | Page 248 of 312
Hardware Reference Manual
Reset Access
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x1 R
0x0 R
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C
0x0 R/W1C