Nonexistent Pins; Electrical Characteristics; Module Stop Function; Interrupt Control Unit - Renesas RA Series Quick Design Manual

Renesas RA Family RA4 Quick Design Guide

10.6 Nonexistent Pins

Each RA4 MCU group is available in multiple package sizes, with different total pin counts. For any package
smaller than the largest package for that MCU group (typically 100 pins or 144 pins), set the corresponding
bits of nonexistent ports in the PDR register to "1" (output) and in the PODR register to "0". The user can see
which ports are available on each MCU package by reviewing the "Specifications of I/O Ports" table in the I/O
Ports section of the Hardware User's Manual. For example, pins 0 and 1 on port 1 are only available on 176
pin packages. Note that no additional handling of nonexistent pins is required.

10.7 Electrical Characteristics

Normal GPIO ports typically require CMOS level inputs (High ≥ 0.8 * Vcc, Low ≤ 0.2 * Vcc). Some GPIO
ports have Schmitt Trigger inputs, which have slightly different input requirements. See the Hardware User's
Manual section "Electrical Characteristics" for more information.

11. Module Stop Function

To maximize power efficiency, the RA4 series of MCUs allow on-chip peripherals to be stopped individually
by writing to the Module Stop Control Registers (MSTPCRi, i=A, B, C, D, E). Once a module stops, access to
the module registers is not possible.
After a reset, most of the modules are placed in module-stop state, except for DMAC, DTC, and SRAM. See
Hardware User's Manual for details.
Before accessing any of the registers for a peripheral, it must be enabled by taking it out of stop mode by
writing a '0' to the corresponding bit in the MSTPCRi register.
Peripherals may be stopped by writing a '1' to the proper bit in the MSTPCRi register.
HAL drivers in Renesas FSP handle module start/stop function automatically.

12. Interrupt Control Unit

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC, DTC, and DMAC
modules. The ICU also controls non-maskable interrupts. Figure 32 shows an example of the ICU
specifications, and Figure 33 shows an example of the ability to raise the IRQi event from the I/O pins. Refer
to the Hardware User's Manual for details for each RA4 MCU Group.
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Jul.21.21