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M
1
6
C
2 /
9
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o r
u
p
6. Processor Mode
The MCU supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers.
Processor Mode Register 0
b7
b6
b5
b4
0
0
0 0
NOTES:
1. Set the PM0 register after the PRC1 bit in the PRCR register is set to 1 (write enable).
Processor Mode Register 1
b7
b6
b5
b4
0
0 0
NOTES:
1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to 1 (write enable).
2. To access the two 2K-byte data spaces in data block A and data block B, set the PM10 bit to 1. The PM10
bit is not available in mask version.
3. When the FMR01 bit in the FMR0 register is set to 1 (enables CPU rewrite mode), the PM10 bit is
automatically set to 1.
4. Set the PM12 bit to 1 by program. (Writing 0 by program has no effect)
5. When the PM17 bit is set to 1 (wait state), one wait is inserted when accessing the internal RAM or the
internal ROM.
Figure 6.1 PM0 Register and PM1 Register
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
(1)
Symbol
b3
b2
b1
b0
0
0 0
PM0
Bit Symbol
(b2-b0)
PM03
(b7-b4)
(1)
b3
b2
b1
b0
Symbol
0
1
PM1
Bit Symbol
PM10
(b1)
PM12
(b3)
(b6-b4)
PM17
page 44
f o
4
5
8
Address
After Reset
0004
00
16
Bit Name
Reserved bit
Set to 0
Software reset bit
Reserved bit
Set to 0
Address
After Reset
0005
00001000
16
Bit Name
Flash data block access
0: Disabled
(2)
bit
1: Enabled
Reserved bit
Set to 0
Watchdog timer function
0 : Watchdog timer interrupt
select bit
1 : Watchdog timer reset
Reserved bit
Set to 1
Reserved bit
Set to 0
0 : No wait state
(5)
Wait bit
1 : Wait state (1 wait)
16
Function
The MCU is reset when
this bit is set to 1. When read,
its content is 0.
2
Function
(3)
(4)
6. Processor Mode
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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